Memory address permutation apparatus

Claim 1

In a memory system with memory space arranged in logical data words with bit positions of any of the logical data words stored in a plurality of memory elements where the memory elements are each accessed through a different one of a plurality of decoders by an actual address of a data location in the element, new apparatus for preventing faulty data bits at the same actual address in two different memory elements from being used to store different bit positions of a given logical data word comprising: address means for providing a logical address for said given logical data word; a single address translation means for translating said logical address to all actual addresses of data bits accessed by each of said plurality of decoders, said translation means including permutation means for substituting address bits of said logical address with address bits of another logical address in the memory space in the translating of the logical address to the actual address for one of said two different memory elements so that the actual address for bit position of the logical data word stored in said one of said two different memory elements differs both from the actual address for the bit position stored in the other of said two different memory elements and from the actual address of other bit positions in said logical data word; distribution means for supplying to each of said decoders the appropriate one of said actual addresses produced by said translation means whereby the alignment of the faulty data bits in said given logical address can be eliminated without the use of spare memory elements.