US3812336A
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Dynamic address translation scheme using orthogonal squares
Assignee: International Business Machines Corp
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Filing: 1972-12-18
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Granted: 1974-05-21
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Expires: 1992-12-18
Abstract
Abstract This specification describes a scheme for swapping bits between words of a memory when a multiple error condition is detected in any word of the memory by a single error correction and multiple error detection system monitoring the memory. The swapping of the bits between the words is done in terms of orthogonal Latin squares insuring that no combination of any two bits is repeated in the reconfigured words. This insures that with a single swapping of the bits the detected multiple error condition is eliminated and makes it highly unlikely that another double error condition will be produced by the swapping.
Inventors
- 👤 M Hsiao
- 👤 D Bossen
- 👤 C Haugh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:26
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
234 words
In a memory unit made up of a plurality of arrays each array containing all the bits for one bit position in the memory unit and having a decoder to select one of the bits in each of the arrays to form an information unit in the memory when an identical information unit selection address is supplied to each of the arrays, the improvement comprising: a single error correction multiple error detection means for the correction of a single error in the information units of the memory and for an output signal when a multiple error condition is detected in an information unit; a different shift register means associated with each of the decoders and coupled to said single error correction multiple error detection means for responding to said output caused by the detection of a multiple error condition in an information unit by changing the data stored in the shift register means; and an Exclusive OR circuit means for supplying an output to each of the inputs of the decoder with which it is associated and receiving one input from one of the stages of the shift register with which the decoder is associated and another input from a digit of the information unit selection address whereby the changes in data stored in the shift registers changes the bits making up the flawed information unit so as to eliminate the multiple error detected.
Claim 2
Dependent Claim
234 words
In a memory unit made up of a plurality of arrays each array containing all the bits for one bit position in the memory unit and having a decoder to select one of the bits in each of the arrays to form an information unit in the memory when an identical information unit selection address is supplied to each of the arrays, the improvement comprising: a single error correction multiple error detection means for the correction of a single error in the information units of the memory and for an output signal when a multiple error condition is detected in an information unit; a different shift register means associated with each of the decoders and coupled to said single error correction multiple error detection means for responding to said output caused by the detection of a multiple error condition in an information unit by changing the data stored in the shift register means; and an Exclusive OR circuit means for supplying an output to each of the inputs of the decoder with which it is associated and receiving one input from one of the stages of the shift register with which the decoder is associated and another input from a digit of the information unit selection address whereby the changes in data stored in the shift registers changes the bits making up the flawed information unit so as to eliminate the multiple error detected.
Claim 3
Dependent Claim
25 words
The memory unit of claim 1 wherein said shift registers are Galois counters each storing a different binary number in a Galois field transformation sequence.
Claim 4
Dependent Claim
16 words
The structure of claim 2 wherein said Galois field counters are a linear feedback shift registers.
Claim 5
Dependent Claim
161 words
A memory unit made up of a plurality of arrays with each array having a decoder to select bits from the arrays to form an information unit of the memory when an identical binary number called an unit selection address is supplied to each of the arrays, the improvement comprising: an error detection and correction means capable of detecting more errors than it can correct in an information unit for providing an output signal when an uncorrectable error condition exists in an information unit; translation means associated with each of the arrays for receiving the information unit selection address and in response thereto supplying to a different binary number in Galois field transformation sequence to each of the decoders; and means responsive to said output signal of the error detection and correction means for changing the binary numbers supplied to the decoders by the translation means to different numbers in the Galois field transformation sequence when an uncorrectable error is detected.
Claim 6
Dependent Claim
161 words
A memory unit made up of a plurality of arrays with each array having a decoder to select bits from the arrays to form an information unit of the memory when an identical binary number called an unit selection address is supplied to each of the arrays, the improvement comprising: an error detection and correction means capable of detecting more errors than it can correct in an information unit for providing an output signal when an uncorrectable error condition exists in an information unit; translation means associated with each of the arrays for receiving the information unit selection address and in response thereto supplying to a different binary number in Galois field transformation sequence to each of the decoders; and means responsive to said output signal of the error detection and correction means for changing the binary numbers supplied to the decoders by the translation means to different numbers in the Galois field transformation sequence when an uncorrectable error is detected.
Claim 7
Dependent Claim
134 words
The memory unit of claim 4 wherein said translation means comprises: a different linear feedback shift register means for each decoder coupled to the error detection and correction means for responding to said output signal caused by the detection of uncorrectable errors in an information unit by changing the data stored in the linear feedback shift register means; and an Exclusive OR circuit for supplying an output to each of the inputs of the decoder and receiving one input from one of the stages of the shift register with which the decoder is associated and another input from the digit of the information unit selection address for the memory unit whereby upon detection of an uncorrectable error data in the shift register is changed so as to change bits making up the flawed wOrd.
Claim 8
Dependent Claim
20 words
The memory unit of claim 5 wherein said error correction means is a single error correction, multiple error detection system.
Claim 9
Dependent Claim
18 words
The memory unit of claim 6 wherein each array supplies one bit for a word of the memory.
Claim 10
Dependent Claim
30 words
The memory unit of claim 7 wherein the data in one of the shift registers is zero and the shift register is not changed when a multiple error is detected.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-05-20 | 1977-11-19 | 1978-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-05-20 | 1981-11-19 | 1982-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-05-20 | 1985-11-19 | 1986-05-21 | $7700.00 | Window Closed / Lapsed |