Memory system with selective assignment of spare locations

Claim 2

In a data processing system having a central processing unit including a memory input bus and a memory output bus each having K lines for transferring a data word consisting of K bit positions between the CPU and a main memory which comprises a large plurality of memory locations each of which includes K failure independent bit cells with each said location being individually addressable through a memory address bus, and an error correcting system for correcting predetermined types of errors in data words transferred from said main memory, the improvement comprising: a control system for selectively replacing defective bit cells in said main memory, said control system including: a plurality (N) of replacement sections, each of which is associated with a different group of (K/N) bit positions of said data word, each said section comprising a separate failure independent memory for each bit position of said group, each said memory element comprising a plurality of individually addressable bit cells; means for partially addressing said memory element of each said replacement section with a first subset of address signals directly from said main memory address bus, each said replacement section being further characterized by a writable index which includes a plurality of control data storage locations which are individually addressable by a second subset of address signals from said main memory address bus to provide at least a third subset of address signals which when combined with said first subset of address signals comprise the complete address for said memory element, and means for developing control signals for each said writable index based on the distribution of defective bit cells in each data word storage location of said main memory.

Claim 3

The system recited in claim 1 in which each said data word comprises 144 bit positions, said memory input bus comprises 144 lines, said memory output bus comprises 144 lines, said memory address bus comprises 22 lines, said relatively large plurality of memory storage locations comprises 64 2 K addressable storage locations, said plurality of replacement sections comprises 36 sections, said group of bit positions associated with each section comprises 4 bit positions of said data word, said plurality of individually addressable bit cells of each said failure independent memory element comprises 64K, said first subset of address signals comprises 16 signals, said plurality of control data storage locations comprises 4K positions, and said second subset of address signals comprises 16 signals.

Claim 4

The system recited in claim 1 in which said means for developing control signals for each said writable index includes: (a) means for identifying each defective bit cell in each of said plurality of memory locations; and (b) means for analyzing the pattern of defects in said main memory in accordance with a predetermined control strategy which reflects the power of said ECC system; and said control system further includes means for transferring developed control signals to said writable index of each said replacement section.

Claim 5

The system recited in claim 3 in which said means for transferring includes means for addressing each said index with said second subset of address signals to store said developed control signals in each said index at locations which are address related to main memory locations.

Claim 6

The system recited in claim 4 in which each said section includes decoding means connected between the output of said index and each said separate memory element.

Claim 7

The system recited in claim 5 in which said decoding means is operable to selectively connect at least one of said separate memory elements to at least one line of said memory input bus and said memory output bus to cause a bit cell of said connected element defined by said first subset of address signals to logically replace an identified defective bit cell in said main memory which is associated with a bit position of an addressed data word and the section containing said selectively connected memory element.

Claim 8

The system recited in claim 5 in which a portion of the output of said writable index is used as a portion of an address along with said first subset of address signals to address said memory elements.

Claim 9

In a data processing system having a central processing unit (CPU), a main memory system (MMS) having a large plurality of individually addressable storage locations each of which comprises K failure independent bit storage cells for storing data words consisting of K bit positions that are processed by said data processing system, and an error correcting system (ECC) for automatically correcting errors of predetermined types in a data word transferred from said MMS to said CPU, the improvement comprising: a secondary memory system (SMS) connectable between said CPU and said MMS and operable to selectively assign failure independent bit storage cells in said SMS to replace previously identified defective bit cell positions in said MMS, said SMS being characterized by a writable index having a plurality of addressable storage locations each of which has a predetermined relationship to a group of storage locations in said MMS and each of which contains control data to control the assignment of a secondary bit cell for a defective bit cell in said MMS in accordance with (1) said predetermined addressing relationship, (2) the distribution of defective bit cells in said MMS, and (3) the power of said ECC system, in order to minimize the number of secondary bit cells that are assigned and maximize the number of data words transferred to said CPU before an uncorrectable error is encountered.

Claim 10

In a data processing system having a central processing unit (CPU), a main memory system (MMS) having a large plurality of individually addressable storage locations each of which comprises K failure independent bit storage cells for storing data words consisting of K bit positions that are processed by said data processing system, and an error correcting system (ECC) for automatically correcting errors of predetermined types in a data word transferred from said MMS to said CPU, the improvement comprising: a secondary memory system (SMS) connectable between said CPU and said MMS and operable to selectively assign failure independent bit storage cells in said SMS to replace previously identified defective bit cell positions in said MMS, said SMS being characterized by a writable index having a plurality of addressable storage locations each of which has a predetermined relationship to a group of storage locations in said MMS and each of which contains control data to control the assignment of a secondary bit cell for a defective bit cell in said MMS in accordance with (1) said predetermined addressing relationship, (2) the distribution of defective bit cells in said MMS, and (3) the power of said ECC system, in order to minimize the number of secondary bit cells that are assigned and maximize the number of data words transferred to said CPU before an uncorrectable error is encountered.

Claim 11

A memory system for storing a plurality of data words each of which includes a plurality of data bit positions and a plurality of check bit positions containing error correcting check bits, an error correcting system associated with said memory system to correct predetermined error types that occur in said data words during readout from said memory by processing said check bits, said memory system comprising: a main memory having a relatively large number of individually addressable data word storage locations each of which comprises a plurality of failure independent bit cells, predetermined ones of which have been identified as being defective; a secondary memory having a relatively small number of individually addressable storage locations each of which comprises a plurality of failure independent bit cells; means for identifying bit cells in said main memory which are defective and control means for logically substituting bit cells in said secondary memory for selected areas in said main memory which contain identified defective bit cells; said control means being characterized by a writable index comprising a third memory which is addressable with a first subset of signals from said main memory addressing bus to provide a plurality of field control signals, one field of which is combined with a second subset of signals from said main memory address bus to cause the logical substitution of a defective said bit cell in said main memory with a good bit cell in said secondary memory, said field control signals being further operable to reconfigure portions of said secondary memory to permit each bit location of a data word to be assigned to more than one said portion, said system being further characterized by said field control signals reflecting an analysis of the location of each defective cell in said main memory and the power of said error correcting system in order to minimize the logical replacement of defective bit cells and maximize the number of data words which can be transferred from memory before an uncorrectable error is encountered by said error correcting system.

Claim 12

A memory system for storing a plurality of data words each of which includes a plurality of data bit positions and a plurality of check bit positions containing error correcting check bits, an error correcting system associated with said memory system to correct predetermined error types that occur in said data words during readout from said memory by processing said check bits, said memory system comprising: a main memory having a relatively large number of individually addressable data word storage locations each of which comprises a plurality of failure independent bit cells, predetermined ones of which have been identified as being defective; a secondary memory having a relatively small number of individually addressable storage locations each of which comprises a plurality of failure independent bit cells; means for identifying bit cells in said main memory which are defective and control means for logically substituting bit cells in said secondary memory for selected areas in said main memory which contain identified defective bit cells; said control means being characterized by a writable index comprising a third memory which is addressable with a first subset of signals from said main memory addressing bus to provide a plurality of field control signals, one field of which is combined with a second subset of signals from said main memory address bus to cause the logical substitution of a defective said bit cell in said main memory with a good bit cell in said secondary memory, said field control signals being further operable to reconfigure portions of said secondary memory to permit each bit location of a data word to be assigned to more than one said portion, said system being further characterized by said field control signals reflecting an analysis of the location of each defective cell in said main memory and the power of said error correcting system in order to minimize the logical replacement of defective bit cells and maximize the number of data words which can be transferred from memory before an uncorrectable error is encountered by said error correcting system.

Claim 13

In a memory system which has a main memory for storing a relatively large number of data words at individually addressable locations, each of which comprises a plurality of failure independent bit cells for storing a data word along with error correcting check characters, and a secondary memory which has a relatively small number of addressable data word locations, each of which comprises a corresponding plurality of failure independent bit cells, and a writable index having a plurality of addressable storage locations, each of which stores a unique group of control signals, a method of assigning spare bit cells in said secondary memory as replacements for defective bit cells in said main memory, comprising: addressing each location in main memory to determine defective bit cells; storing an indication of each defective bit cell in said main memory; analyzing the defective bit cell distribution for each data word; developing memory control signals based on said defective bit cell distribution and the error types which are correctable by an associated ECC system; transferring, prior to storing data in said main memory, said memory control signals to said writable index to store said control signals at locations which have a predetermined addressing relationship to the addresses of main memory; and transferring a data word to said main memory or from said main memory by addressing a location in said main memory while simultaneously addressing said index and said secondary memory with different subsets of address signals employed to address said location in said main memory whereby said control signals stored in said writable index cause the selective replacement of defective bit cells in said main memory with addressed bit cells of said secondary memory to permit storage and retrieval of data words in said memory system with a minimum of errors.

Claim 14

In a memory system which has a main memory for storing a relatively large number of data words at individually addressable locations, each of which comprises a plurality of failure independent bit cells for storing a data word along with error correcting check characters, and a secondary memory which has a relatively small number of addressable data word locations, each of which comprises a corresponding plurality of failure independent bit cells, and a writable index having a plurality of addressable storage locations, each of which stores a unique group of control signals, a method of assigning spare bit cells in said secondary memory as replacements for defective bit cells in said main memory, comprising: addressing each location in main memory to determine defective bit cells; storing an indication of each defective bit cell in said main memory; analyzing the defective bit cell distribution for each data word; developing memory control signals based on said defective bit cell distribution and the error types which are correctable by an associated ECC system; transferring, prior to storing data in said main memory, said memory control signals to said writable index to store said control signals at locations which have a predetermined addressing relationship to the addresses of main memory; and transferring a data word to said main memory or from said main memory by addressing a location in said main memory while simultaneously addressing said index and said secondary memory with different subsets of address signals employed to address said location in said main memory whereby said control signals stored in said writable index cause the selective replacement of defective bit cells in said main memory with addressed bit cells of said secondary memory to permit storage and retrieval of data words in said memory system with a minimum of errors.

Claim 15

The method recited in claim 10 in which said memory control signals transferred to said index result in a minimum number of defective cells being replaced while maximizing the number of data words that are transferred from said main memory before an error is encountered that is uncorrectable by an associated error correcting system.