US4028539A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory with error detection and correction means
Assignee: Digital Equipment Corp
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Filing: 1975-11-20
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Granted: 1977-06-07
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Expires: 1995-11-20
Abstract
Abstract The invention relates to a memory device which initially consists of a number of modules which can be exchanged and wherein no non-correctable storage errors are present. If such errors occur at a later stage, the address of the detective module is applied to an inversion device which is connected between an address input line and the actual memory device. This address actuates the inversion device such that the relevant memory unit becomes the last one in the sequence of memory units. By blocking the highest address, a memory device having a substantially unchanged capacity can thus be automatically realized. By replacement of the defective module at a later stage, the original capacity can be restored. If a second module fails after the first module has become defective, the sequence can be modified again etc., with the result that each time an as large as possible number of modules of the memory device can be addressed in a consecutive sequence.
Inventors
- 👤 Pieter Anton Jacobs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:56
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
223 words
A memory comprising: a first plurality of memory units, a first input address line connected to said memory units for delivering a first partial address thereto, said first plurality of memory units having valid partial addresses in a first partial address sequence from a specified first to a specified second memory unit; a second input address line connected to said memory units for addressing individual bits of one of said memory units; a data input register connected to said plurality of memory units; a data output register connected to said plurality of memory units; a detection device connected to said data output register for detecting a non correctable storage error and producing an output signal; an inversion device connected to said first input address line for inverting predetermined address bits, thereby allowing addressing of said first plurality of memory units in a second partial address sequence starting from a third memory unit; an inversion control device, having an input connected to said detection device, and an output connected to said inversion device for activating said inversion device; and blocking means for blocking addressing of ones of a second plurality of memory units beyond a predetermined fourth memory unit, said blocking means and said inversion control device being linked for blocking addressing of a faulty memory unit in said second plurality of memory units.
Claim 2
Dependent Claim
223 words
A memory comprising: a first plurality of memory units, a first input address line connected to said memory units for delivering a first partial address thereto, said first plurality of memory units having valid partial addresses in a first partial address sequence from a specified first to a specified second memory unit; a second input address line connected to said memory units for addressing individual bits of one of said memory units; a data input register connected to said plurality of memory units; a data output register connected to said plurality of memory units; a detection device connected to said data output register for detecting a non correctable storage error and producing an output signal; an inversion device connected to said first input address line for inverting predetermined address bits, thereby allowing addressing of said first plurality of memory units in a second partial address sequence starting from a third memory unit; an inversion control device, having an input connected to said detection device, and an output connected to said inversion device for activating said inversion device; and blocking means for blocking addressing of ones of a second plurality of memory units beyond a predetermined fourth memory unit, said blocking means and said inversion control device being linked for blocking addressing of a faulty memory unit in said second plurality of memory units.
Claim 3
Dependent Claim
51 words
The device defined in claim 1, wherein said inversion device comprises: a signal input terminal; two differential amplifiers each having an input connected to said input terminal, and an output; and logic means connected to said outputs of said differential amplifiers for controllably inverting the signal supplied on said input terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-06 | 1980-12-06 | 1981-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-06 | 1984-12-06 | 1985-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-06 | 1988-12-06 | 1989-06-07 | $7700.00 | Window Closed / Lapsed |