US3917933A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error logging in LSI memory storage units using FIFO memory of LSI shift registers
Assignee: Unisys Corp
•
Filing: 1974-12-17
•
Granted: 1975-11-04
•
Expires: 1994-12-17
Abstract
Abstract A maintenance procedure comprising a method of and an apparatus for storing information identifying the location of one or more defective bits, i.e., a defective memory element, a defective storage device or a failure, in a single-error-correcting semiconductor main storage unit (MSU) comprised of a plurality of replaceable large scale integrated (LSI) bit planes. The method utilizes an error logging store (ELS) that is comprised of a plurality of word-group-associated registers which hold the address data that identifies the replaceable LSI bit planes of the MSU in which a correctable error has been detected. After each detection of a correctable error, the address data is compared to address data already stored in the ELS. If the comparison indicates that it is new address data, i.e., that that bit plane has not previously caused a correctable error, the address data is entered into the ELS, shifting all previous entries one stage. After a predetermined number of defective bit plane addresses, i.e., address data, are stored therein a signal is generated to alert the machine operator to schedule preventive maintenance of the MSU by replacing the defective bit planes. By statistically determining the number of allowable failures, i.e., the number of correctable failures that may occur before the expected occurrence of a non-correctable double bit error, preventive maintenance may be scheduled only as required by the particular MSU.
Inventors
- 👤 James H Scheuneman
- 👤 John R Trost
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:14
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/073; G06F11/0766; G06F11/0772; G06F11/0787
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
598 words
In a data processing system that includes an LSI semiconductor memory system that is configured into M word groups of N bit planes per word group and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout and single error correction circuitry coupled to said memory system for generating upon the detection of each correctable error in said memory system an error word that is associated with only the one of the N bit planes of the one of the M word groups in which the correctable error is detected, said error word comprising a single tag bit 2T and S syndrome bits, said tag bit indicating that a correctable error has occurred in said one of the M word groups in the one of the N bit planes that is identified by said S syndrome bits, and a memory address register for addressing said LSI semiconductor memory system and holding the W ordered bits that address the one selected word group and the X ordered bits that address the one selected bit on each bit plane in the one selected word group, the improvement comprising: a word group address buffer comprised of 1 + W shift registers, each of Y ordered stages in length, the like-ordered stages of said 1 + W shift registers arranged to form Y address registers each of 1 + W stages in length; a bit plane address buffer comprised of S shift registers, each of Y ordered stages in length, the like-ordered stages of said S shift registers arranged to form Y syndrome registers, each of S stages in length; a word group address register of 1 + W ordered stages for receiving the W ordered bits of said word group address from said memory address register and coupling each ordered bit of said word group address to the like-ordered one of said W shift registers of said word group address buffer, and for receiving said tag bit 2T from said single error correcting circuitry and coupling said tag bit to said 1 shift register of said word group address buffer; a bit plane address register of S ordered stages for receiving the S ordered bits of said syndrome bits from said single error correction circuitry and coupling each ordered bit of said S syndrome bits to the like-ordered one of said S shift registers of saId bit plane address buffer; comparator means for comparing the tag bit and the word group address stored in each of said Y address registers of said word group address buffer to the tag bit and to the word group address stored in said word group address register and generating a miss signal only if no match is found; means coupled to said comparator means for shifting the contents of each of the Y address registers of said word group address buffer and the contents of each of the S syndrome registers of said bit plane address buffer one stage and loading the contents of said word group address register into the first address register of said word group address buffer and the contents of said bit plane address register into the first syndrome register of said bit plane address buffer when activated by said miss signal; means coupled to the 1 shift register stage of one of the Y address registers of said word group address buffer for monitoring the tag bit stored therein and alerting the machine operator that preventive maintenance should be scheduled.
Claim 2
Dependent Claim
598 words
In a data processing system that includes an LSI semiconductor memory system that is configured into M word groups of N bit planes per word group and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout and single error correction circuitry coupled to said memory system for generating upon the detection of each correctable error in said memory system an error word that is associated with only the one of the N bit planes of the one of the M word groups in which the correctable error is detected, said error word comprising a single tag bit 2T and S syndrome bits, said tag bit indicating that a correctable error has occurred in said one of the M word groups in the one of the N bit planes that is identified by said S syndrome bits, and a memory address register for addressing said LSI semiconductor memory system and holding the W ordered bits that address the one selected word group and the X ordered bits that address the one selected bit on each bit plane in the one selected word group, the improvement comprising: a word group address buffer comprised of 1 + W shift registers, each of Y ordered stages in length, the like-ordered stages of said 1 + W shift registers arranged to form Y address registers each of 1 + W stages in length; a bit plane address buffer comprised of S shift registers, each of Y ordered stages in length, the like-ordered stages of said S shift registers arranged to form Y syndrome registers, each of S stages in length; a word group address register of 1 + W ordered stages for receiving the W ordered bits of said word group address from said memory address register and coupling each ordered bit of said word group address to the like-ordered one of said W shift registers of said word group address buffer, and for receiving said tag bit 2T from said single error correcting circuitry and coupling said tag bit to said 1 shift register of said word group address buffer; a bit plane address register of S ordered stages for receiving the S ordered bits of said syndrome bits from said single error correction circuitry and coupling each ordered bit of said S syndrome bits to the like-ordered one of said S shift registers of saId bit plane address buffer; comparator means for comparing the tag bit and the word group address stored in each of said Y address registers of said word group address buffer to the tag bit and to the word group address stored in said word group address register and generating a miss signal only if no match is found; means coupled to said comparator means for shifting the contents of each of the Y address registers of said word group address buffer and the contents of each of the S syndrome registers of said bit plane address buffer one stage and loading the contents of said word group address register into the first address register of said word group address buffer and the contents of said bit plane address register into the first syndrome register of said bit plane address buffer when activated by said miss signal; means coupled to the 1 shift register stage of one of the Y address registers of said word group address buffer for monitoring the tag bit stored therein and alerting the machine operator that preventive maintenance should be scheduled.
Claim 3
Dependent Claim
21 words
The improvement of claim 1 in which: M 128 N 45 B 1,024 S 6 W 7 X 10 Y 16.
Claim 4
Dependent Claim
541 words
In a data processing system that includes an LSI semiconductor memory system that is configured into a plurality of word groups each having a plurality of bit planes and a plurality of bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout and single error correction circuitry coupled to said memory system for generating upon the detection of each correctable error in said memory system an error word that is associated with one of the bit planes in which the correctable error is detected, said error word comprising a single tag bit 2T and a plurality of syndrome bits, said tag bit indicating that a correctable error has occurred in the one of the bit planes that is identified by said plurality of syndrome bits, and a memory address register for addressing said LSI semiconductor memory system and holding the ordered bits that address the one selected word group and the ordered bits that address the one selected bit on each bit plane in the one selected word. group, the improvement comprising: a word group address buffer comprised of a plurality of registers, the like-ordered stages of said shift registers arranged to form a plurality of address registers; a bit plane address buffer comprised of a plurality of shift registers, the like-ordered stages of said shift registers arranged to form a plurality of syndrome registers; a word group address register having a plurality of ordered stages for receiving the ordered bits of said word group address from said memory address register and coupling each ordered bit of said word group address to the like-ordered shift register of said word group address buffer, and for receiving said tag bit 2T from said single error correcting circuitry and coupling said tag bit to the like-ordered shift register of said word group address buffer; a bit plane address register having a plurality of ordered stages for receiving the ordered bits of said syndrome bits from said single error correction circuitry and coupling each ordered bit of said syndrome bits to the like-ordered shift register of said bit plane address buffer; comparator means for comparing the tag bit and the word group address bits stored in each of said address registers of said word group address buffer to the tag bit and the word group address bits stored in said word group address register and generating a miss signal only if no match is found; means coupled to said comparator means for shifting the contents of the address registers of said word group address buffer and the contents of the syndrome registers of said bit plane address buffer one stage and loading the contents of said word group address register into the first address register of said word group address buffer and the contents of said bit plane address register into the first syndrome register of said bit plane address buffer when activated by said miss signal; means coupled to the tag bit holding stage of one of the memory address registers of said word group address buffer for monitoring the tag bit stored therein and alerting the machine operator that preventive maintenance should be scheduled.
Claim 5
Dependent Claim
541 words
In a data processing system that includes an LSI semiconductor memory system that is configured into a plurality of word groups each having a plurality of bit planes and a plurality of bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout and single error correction circuitry coupled to said memory system for generating upon the detection of each correctable error in said memory system an error word that is associated with one of the bit planes in which the correctable error is detected, said error word comprising a single tag bit 2T and a plurality of syndrome bits, said tag bit indicating that a correctable error has occurred in the one of the bit planes that is identified by said plurality of syndrome bits, and a memory address register for addressing said LSI semiconductor memory system and holding the ordered bits that address the one selected word group and the ordered bits that address the one selected bit on each bit plane in the one selected word. group, the improvement comprising: a word group address buffer comprised of a plurality of registers, the like-ordered stages of said shift registers arranged to form a plurality of address registers; a bit plane address buffer comprised of a plurality of shift registers, the like-ordered stages of said shift registers arranged to form a plurality of syndrome registers; a word group address register having a plurality of ordered stages for receiving the ordered bits of said word group address from said memory address register and coupling each ordered bit of said word group address to the like-ordered shift register of said word group address buffer, and for receiving said tag bit 2T from said single error correcting circuitry and coupling said tag bit to the like-ordered shift register of said word group address buffer; a bit plane address register having a plurality of ordered stages for receiving the ordered bits of said syndrome bits from said single error correction circuitry and coupling each ordered bit of said syndrome bits to the like-ordered shift register of said bit plane address buffer; comparator means for comparing the tag bit and the word group address bits stored in each of said address registers of said word group address buffer to the tag bit and the word group address bits stored in said word group address register and generating a miss signal only if no match is found; means coupled to said comparator means for shifting the contents of the address registers of said word group address buffer and the contents of the syndrome registers of said bit plane address buffer one stage and loading the contents of said word group address register into the first address register of said word group address buffer and the contents of said bit plane address register into the first syndrome register of said bit plane address buffer when activated by said miss signal; means coupled to the tag bit holding stage of one of the memory address registers of said word group address buffer for monitoring the tag bit stored therein and alerting the machine operator that preventive maintenance should be scheduled.
Claim 6
Dependent Claim
71 words
The improvement of claim 3 further including means coupled to the tag bit holding stage of the last memory address register of said word group address buffer for monitoring the tag bit stored therein and inhibiting said comparator means from shifting the contents of the address registers of said word group address buffer and the contents of syndrome registers of said bit plane address register when activated by said miss signal.
References Cited (Backward Citations)
US3222653A
Cited
US3444526A
Cited
US3633175A
Cited
US3697949A
Cited
US3794819A
Cited
US3803560A
Cited
US3872291A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-03 | 1979-05-05 | 1979-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-03 | 1983-05-05 | 1983-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-03 | 1987-05-05 | 1987-11-04 | $7700.00 | Window Closed / Lapsed |