US3794819A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error correction method and apparatus
Assignee: Advanced Memory Systems Inc
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Filing: 1972-07-03
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Granted: 1974-02-26
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Expires: 1992-07-03
Abstract
Abstract An improved error correction method and apparatus which is capable of correcting single digital errors and capable of detecting multiple errors. In accordance with the invention as used in a memory system, a plurality of storage cards are used, each organized so as to provide a single data output and a data valid output, the data valid output being determined as a result of a parity check of a multiple bit memory signal from which the data output is selected as a result of further addressing. Similarly, one further storage card is used to provide a single parity check signal for the data signals from the other storage cards and to provide a parity valid signal in the same manner as the data valid signals. By applying these various signals to a gating system, an error in any one of the signals may be detected, and if in a data signal, may be corrected. Multiple errors may similarly be detected and noted by the provision of a signal indicating such multiple errors.
Inventors
- 👤 A Berding
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:05
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
310 words
Apparatus for detecting and correcting errors occurring in desired digital signals having a first plurality of data bits and a parity bit associated therewith comprising: in plurality, means for selecting a second plurality of digital signals from a greater plurality of digital signals, each of said second plurality of digital signals having therein a parity check bit which may be used to check the parity of the remainder of each of said second plurality of digital signals; in plurality, means for checking the parity of said second plurality of digital signals and for providing a valid signal indicative of the results of the parity check; in plurality, means for selecting one bit of said desired digital signal from each of said second plurality of digital signals, whereby all of said data bits and said parity bit of said desired digital signal are selectable by the plurality of said last named means; means for providing a parity check on said desired digital signal and for providing a parity check signal indicative of the results of the parity check; means for sensing the simultaneous occurrence of a failure to obtain a parity check as indicated by said parity check signal and a single valid signal indicating the failure to obtain a parity check in said respective one of said second plurality of digital signals, and for providing an output in response thereby; means responsive to the output of said last named means for inverting the bit of said desired digital signal selected from the one of said second plurality of digital signals for which said valid signal indicates a failure to obtain a parity check; and means for providing an output signal indicative of the occurrence of at least two of said valid signals indicating failure to obtain a parity check in the respective ones of said second pluralities of digital signals.
Claim 2
Dependent Claim
310 words
Apparatus for detecting and correcting errors occurring in desired digital signals having a first plurality of data bits and a parity bit associated therewith comprising: in plurality, means for selecting a second plurality of digital signals from a greater plurality of digital signals, each of said second plurality of digital signals having therein a parity check bit which may be used to check the parity of the remainder of each of said second plurality of digital signals; in plurality, means for checking the parity of said second plurality of digital signals and for providing a valid signal indicative of the results of the parity check; in plurality, means for selecting one bit of said desired digital signal from each of said second plurality of digital signals, whereby all of said data bits and said parity bit of said desired digital signal are selectable by the plurality of said last named means; means for providing a parity check on said desired digital signal and for providing a parity check signal indicative of the results of the parity check; means for sensing the simultaneous occurrence of a failure to obtain a parity check as indicated by said parity check signal and a single valid signal indicating the failure to obtain a parity check in said respective one of said second plurality of digital signals, and for providing an output in response thereby; means responsive to the output of said last named means for inverting the bit of said desired digital signal selected from the one of said second plurality of digital signals for which said valid signal indicates a failure to obtain a parity check; and means for providing an output signal indicative of the occurrence of at least two of said valid signals indicating failure to obtain a parity check in the respective ones of said second pluralities of digital signals.
Claim 3
Dependent Claim
50 words
The apparatus of claim 1 further comprised of a means for providing an output signal indicative of the occurrence of a failure to obtain a parity check in said desired digital signal when all of said valid signals indicate a parity check of said respective second pluralities of digital signals.
Claim 4
Dependent Claim
250 words
A means for detecting and correcting errors in digital information having a plurality of bits, one of which is a parity check bit for the remainder of said digital information accessed from a memory, comprising: means for addressing said memory to provide a first plurality of digital signals and a parity check signal therefore; means for performing a parity check on said first plurality of digital signals; means for addressing said first plurality of digital signals to select one of said last named digital signals providing one bit of said digital information; all of said previously named means being taken in plurality so as to be capable of collectively providing said plurality of bits of said digital information, each of said last named bits having a valid signal associated therewith indicative of the results of the parity check performed on the respective first plurality of digital signals; means for performing a parity check on said digital information; means for determining the simultaneous occurrence of a failure to obtain a parity check of said digital information and a failure to obtain a parity check of one of said first plurality of digital signals; means for inverting the one of said digital signals selected from the one of said first plurality of digital signals on which a parity check was not obtained; and means for providing an output signal responsive to the occurrence of a failure to obtain a parity check in at least two of said first plurality of digital signals.
Claim 5
Dependent Claim
250 words
A means for detecting and correcting errors in digital information having a plurality of bits, one of which is a parity check bit for the remainder of said digital information accessed from a memory, comprising: means for addressing said memory to provide a first plurality of digital signals and a parity check signal therefore; means for performing a parity check on said first plurality of digital signals; means for addressing said first plurality of digital signals to select one of said last named digital signals providing one bit of said digital information; all of said previously named means being taken in plurality so as to be capable of collectively providing said plurality of bits of said digital information, each of said last named bits having a valid signal associated therewith indicative of the results of the parity check performed on the respective first plurality of digital signals; means for performing a parity check on said digital information; means for determining the simultaneous occurrence of a failure to obtain a parity check of said digital information and a failure to obtain a parity check of one of said first plurality of digital signals; means for inverting the one of said digital signals selected from the one of said first plurality of digital signals on which a parity check was not obtained; and means for providing an output signal responsive to the occurrence of a failure to obtain a parity check in at least two of said first plurality of digital signals.
Claim 6
Dependent Claim
46 words
The apparatus of claim 3 further comprised of a means for providing an output signal responsive to the occurrence of a failure to obtain a parity check in said digital information when a parity check of each of said first plurality of digital signals is obtained.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-25 | 1977-08-27 | 1978-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-25 | 1981-08-27 | 1982-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-25 | 1985-08-27 | 1986-02-26 | $7700.00 | Window Closed / Lapsed |