Online realignment of memory faults

Claim 1

A memory system comprising in combination: having a number of memory chips arranged in a matrix of N rows and M columns, each said chip having K×L individually addressable data bit positions; K×L×N memory addresses, each of which comprises M bit positions; a buffer for storing words each comprising M bit positions: means for connecting the write input and the read output of each of said chip in each said column of said memory matrix to one of the buffer storage positions associated with each one of said memory columns; a source of changeable control signals, and data steering logic means connected to said source and said buffer for changing the connective relationship of said buffer storage positions associated with each bit position of said buffer relative to the position of said chips in the corresponding memory matrix column in response to said control signals, said control signals causing said relationship of said chips to said N buffer positions to be altered when said control signals are changed; said source producing first and second control signals respectively representing an initial premute vector and a new permute vector, said data steering logic means receiving said first control signal during a read operation when the read output of each said chip at a given address is connected to said associated buffer storage positions, said data steering logic means receiving said second control signal during a write operation when the write input of each said chip at said given address is connected to said associated buffer storage positions; said read and write operations being successive operations and occurring before any address other than said given address is accessed, whereby the same data bits read out of said given address of chips is written back into said given address of chips in permuted form.

Claim 4

A method of operating a memory system having a fault alignment exclusion mechanism which employs an address permute vector for each column of the memory array to change the relationship between each chip in said column and positions of a column buffer, said method being characterized by the following steps: (1) reading out data from one position of each chip in the column to positions of a buffer that are selected by a first permute vector; and (2) writing each bit of said data from said buffer back to the same address position of another chip in the column that is selected by a second permute vector and repeating the above steps for each chip address.

Claim 5

A method of operating a memory system having a fault alignment exclusion mechanism which employs an address permute vector for each column of the memory array to change the relationship between each chip in said column and positions of a column buffer, said method being characterized by the following steps: (1) reading out data from one position of each chip in the column to positions of a buffer that are selected by a first permute vector; and (2) writing each bit of said data from said buffer back to the same address position of another chip in the column that is selected by a second permute vector and repeating the above steps for each chip address.

Claim 6

A method of operating a memory system hyaving a fault alignment exclusion mechanism which employs an address permute vector for each column of the memory array to change the relationship between each chip in said column and positions of a column buffer, said method being characterized by the following steps: (1) determining if an identified error is correctable, and if not: (2) identifying the columns in error; (3) developing a new permute vector for one of said columns in error; (4) transferring data from one address of a first group of chips in said one column to said column buffer of an associated channel in accordance with an old permute vector; (5) transferring data from the said address of a second group of chips in said one column to a column buffer of another channel; (6) transferring data from said column buffers of said associated channel to said first group of chips in accordance with said new permute vector; (7) transferring data from said column buffers of said another channel to said second group of chips in accordance with said new permute vector; (8) advancing the chip address register by 1 and repeating steps 4-7 until all the data in said column is rearranged.

Claim 7

A method of operating a memory system hyaving a fault alignment exclusion mechanism which employs an address permute vector for each column of the memory array to change the relationship between each chip in said column and positions of a column buffer, said method being characterized by the following steps: (1) determining if an identified error is correctable, and if not: (2) identifying the columns in error; (3) developing a new permute vector for one of said columns in error; (4) transferring data from one address of a first group of chips in said one column to said column buffer of an associated channel in accordance with an old permute vector; (5) transferring data from the said address of a second group of chips in said one column to a column buffer of another channel; (6) transferring data from said column buffers of said associated channel to said first group of chips in accordance with said new permute vector; (7) transferring data from said column buffers of said another channel to said second group of chips in accordance with said new permute vector; (8) advancing the chip address register by 1 and repeating steps 4-7 until all the data in said column is rearranged.

Claim 11

A method of operating a memory system having a fault alignment exclusion mechnaism which employs an address permute mechanism which employs an address permute vector for each column of the memory array to change the relationship between each chip in said column and positions of a column buffer, said method being characterized by the following steps: (1) determining if an identified error is correctable, and if not: (2)identifying the columns in error; (3) developing a new permute vector for one of said columns in error; (4) transferring data from one address of the chips in said one column to said column buffer in accordance with an old permute vector; (5) transferring data from said column buffer to said chips in accordnce with said new permute vector; (6) advancing the chip address register by 1 and repeating steps 4 and 5 until all the data in said column is rearranged.

Claim 12

A method of operating a memory system having a fault alignment exclusion mechnaism which employs an address permute mechanism which employs an address permute vector for each column of the memory array to change the relationship between each chip in said column and positions of a column buffer, said method being characterized by the following steps: (1) determining if an identified error is correctable, and if not: (2)identifying the columns in error; (3) developing a new permute vector for one of said columns in error; (4) transferring data from one address of the chips in said one column to said column buffer in accordance with an old permute vector; (5) transferring data from said column buffer to said chips in accordnce with said new permute vector; (6) advancing the chip address register by 1 and repeating steps 4 and 5 until all the data in said column is rearranged.