US5592632A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system
Assignee: Peraso Inc
•
Filing: 1995-06-06
•
Granted: 1997-01-07
•
Expires: 2015-06-06
Abstract
Abstract A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (512K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) Use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) Use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the bus small; 5) Use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) use of programmable control register to facilitate run-time bus reconfiguration; 8) Use of spare bus lines to provide local redundancy for the bus; and 9) Use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained.
Inventors
- 👤 Wing Y. Leung
- 👤 Fu-Chieh Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:38
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/0272; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1032; G06F11/16; G06F11/20; G06F11/2002; G06F11/2007; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; G06F13/4077; G11; G11C; G11C29/00; G11C29/006; G11C29/04; G11C29/08; G11C29/48; G11C29/70; G11C29/76; G11C29/78; G11C29/80; G11C29/808; G11C29/83; G11C29/832; G11C29/88; H04L25/026; H04L5/00; H04L5/14; H04L5/1461; H10; H10P; H10P74/00; H10P74/23; H10P74/232; G06F11/006; G11C2029/0401; G11C2029/0411; G11C29/12; G11C2029/4402; G11C29/81; G11C5/00; G11C5/02; G11C5/04; H04L25/028; H04L25/029; H04L25/0292; H10D; H10D89/00; Y; Y10; Y10S; Y10S257/00; Y10S257/907
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
116 words
A defect-tolerant integrated circuit subsystem comprising: a plurality of modules comprising functional modules and one or more defective modules; a hierarchical bus having a plurality of bus segments connecting to said modules; a plurality of tri-stateable transceivers connected to the hierarchical bus for controlling signal transfer directions on said hierarchical bus and for preventing signal transfer on said hierarchical bus; at least one bus master for controlling operation of said hierarchical bus, said at least one bus master being coupled to said plurality of tri-stateable transceivers; and a plurality of programmable switches connected to the hierarchical bus for isolating said defective modules and defective bus segments of said hierarchical bus from a remainder of said subsystem.
Claim 2
Dependent Claim
116 words
A defect-tolerant integrated circuit subsystem comprising: a plurality of modules comprising functional modules and one or more defective modules; a hierarchical bus having a plurality of bus segments connecting to said modules; a plurality of tri-stateable transceivers connected to the hierarchical bus for controlling signal transfer directions on said hierarchical bus and for preventing signal transfer on said hierarchical bus; at least one bus master for controlling operation of said hierarchical bus, said at least one bus master being coupled to said plurality of tri-stateable transceivers; and a plurality of programmable switches connected to the hierarchical bus for isolating said defective modules and defective bus segments of said hierarchical bus from a remainder of said subsystem.
Claim 3
Dependent Claim
29 words
The subsystem of claim 1, wherein at least one of said module comprises two identification registers for storing an identification code which uniquely identifies said at least one module.
Claim 4
Dependent Claim
19 words
The subsystem of claim 2, wherein said identification registers comprise a nonvolatile memory element and a software programmable register.
Claim 5
Dependent Claim
32 words
A defect-tolerant integrated circuit subsystem as in claim 3, wherein said nonvolatile memory element is programmed to store an identification code only if said at least one module is a functional module.
Claim 6
Dependent Claim
23 words
A defect-tolerant integrated circuit subsystem as in claim 3, wherein said software programmable register is written to during normal operation of the subsystem.
Claim 7
Dependent Claim
31 words
A defect-tolerant integrated circuit subsystem as in claim 3, further comprising means for transferring contents of the nonvolatile memory element to the software programmable register during a resetting of the subsystem.
Claim 8
Dependent Claim
25 words
The subsystem of claim 2, wherein said identification code is a base address for one or more memory blocks of said at least one module.
Claim 9
Dependent Claim
30 words
The subsystem of claim 1, wherein at least one of said modules comprises a control register having a programmable disable bit, which when set, causes said module to be disabled.
Claim 10
Dependent Claim
27 words
The subsystem of claim 1, wherein a plurality of said bus segments are arranged in a grid, said programmable switches being located at vertices of the grid.
Claim 11
Dependent Claim
22 words
The subsystem of claim 9, wherein said modules are coupled to said bus segments at a plurality of locations along the grid.
Claim 12
Dependent Claim
18 words
The subsystem of claim 10, wherein each module is coupled to the grid by one of the transceivers.
Claim 13
Dependent Claim
36 words
The subsystem of claim 11, wherein each of said modules is associated with one of a plurality of groups of said modules, each group of modules being coupled to the grid by one of the transceivers.
Claim 14
Dependent Claim
16 words
The subsystem of claim 9, wherein a plurality of said transceivers are located along the grid.
Claim 15
Dependent Claim
20 words
The subsystem of claim 13, wherein one of said transceivers is located between each adjacent pair of said programmable switches.
Claim 16
Dependent Claim
28 words
The subsystem of claim 14, wherein one or more of said modules is coupled to said grid between one of said transceivers and one of said programmable switches.
References Cited (Backward Citations)
US3585378A
Cited
US3651473A
Cited
US3761879A
Cited
US3849872A
Cited
US3803562A
Cited
US3983537A
Cited
US4038648A
Cited
US4007452A
Cited
US4071887A
Cited
US4063225A
Cited
US4092733A
Cited
US4132869A
Cited
US4188670A
Cited
US4227045A
Cited
US4215430A
Cited
US4355387A
Cited
US4319356A
Cited
US4329685A
Cited
US4379327A
Cited
US4407014A
Cited
US4458297A
Cited
US4467400A
Cited
US4494196A
Cited
US4400794A
Cited
US4639861A
Cited
JPS59212962A
Cited
US4615017A
Cited
US4649384A
Cited
US4605928A
Cited
US4639933A
Cited
US4627058A
Cited
US4703436A
Cited
US4646298A
Cited
US4663758A
Cited
EP0178949A2
Cited
US4736365A
Cited
US4653050A
Cited
US4630355A
Cited
US4707808A
Cited
US4667328A
Cited
US5206832A
Cited
US4823363A
Cited
US4719621A
Cited
US4847615A
Cited
US4906987A
Cited
US4872137A
Cited
US4876700A
Cited
US4680780A
Cited
US4890224A
Cited
US4866508A
Cited
US4943914A
Cited
US4881232A
Cited
US5133064A
Cited
US4926382A
Cited
US5045725A
Cited
US4943966A
Cited
US5055897A
Cited
US5001712A
Cited
US4912633A
Cited
US4985895A
Cited
US4984192A
Cited
US5111434A
Cited
US4970724A
Cited
US5077738A
Cited
US4980765A
Cited
US4974048A
Cited
EP0389203A2
Cited
US5043820A
Cited
US5020020A
Cited
US5379258A
Cited
US5111271A
Cited
US4955020A
Cited
US5187779A
Cited
US5077737A
Cited
US5218686A
Cited
US5161152A
Cited
US5021985A
Cited
US5077596A
Cited
US5128737A
Cited
US5118975A
Cited
US5103424A
Cited
US5252507A
Cited
WO1991016680A1
Cited
US5243703A
Cited
US5261077A
Cited
US5278967A
Cited
US5214657A
Cited
US5159273A
Cited
US5131015A
Cited
US5204836A
Cited
US5247522A
Cited
US5265216A
Cited
US5329559A
Cited
WO1993018459A1
Cited
WO1993018462A1
Cited
US5254883A
Cited
US5268639A
Cited
US5329174A
Cited
US5402388A
Cited
US5434996A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |