US5527745A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating antifuses in an integrated circuit device and resulting structure
Assignee: Crosspoint Solutions Inc
•
Filing: 1993-11-24
•
Granted: 1996-06-18
•
Expires: 2013-11-24
Abstract
Abstract Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.
Inventors
- 👤 Pankaj Dixit
- 👤 William P. Ingram, III
- 👤 Monta R. Holzworth
- 👤 Richard Klein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:41
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/065; H10D; H10D48/00; H10D48/30; H10D48/38; H10D48/381; H10W20/40; H10W20/49; H10W20/491; Y; Y10; Y10S; Y10S438/00; Y10S438/935
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
91 words
In a method of fabricating antifuses in an integrated circuit including the steps of forming contact holes in an oxide layer over a conducting layer of silicon to expose said silicon layer in said contact holes, etching said exposed silicon layer by sputtering prior to the deposition of a noble metal, an improvement comprising forming said contact holes in said oxide layer by etching sidewalls of said contact holes as vertically as possible whereby resputtering oxide from said sidewalls to contaminate said silicon layer is avoided in said sputter etching step.
Claim 2
Dependent Claim
91 words
In a method of fabricating antifuses in an integrated circuit including the steps of forming contact holes in an oxide layer over a conducting layer of silicon to expose said silicon layer in said contact holes, etching said exposed silicon layer by sputtering prior to the deposition of a noble metal, an improvement comprising forming said contact holes in said oxide layer by etching sidewalls of said contact holes as vertically as possible whereby resputtering oxide from said sidewalls to contaminate said silicon layer is avoided in said sputter etching step.
Claim 3
Dependent Claim
23 words
The improvement of claim 1 wherein said contact hole forming step is performed by a reactive ion-etching process in a low pressure atmosphere.
Claim 4
Dependent Claim
39 words
The improvement of claim 1 further comprising etching said silicon layer by sputtering such that less than 100 Angstroms of native silicon dioxide is removed whereby silicide formation between said silicon layer and said noble metal layer is enhanced.
Claim 5
Dependent Claim
97 words
In a method of fabricating antifuses in an integrated circuit including the steps of forming contact holes in an oxide layer over a conducting layer of silicon to expose said silicon layer in said contact holes, depositing a layer of platinum in said contact holes, and reacting said platinum layer with said exposed silicon to form a layer of platinum silicide in said contact holes, an improvement comprising reacting said platinum layer with said exposed silicon in an atmosphere of nitrogen and hydrogen whereby a layer of platinum silicide with a minimal amount of oxygen is present.
Claim 6
Dependent Claim
97 words
In a method of fabricating antifuses in an integrated circuit including the steps of forming contact holes in an oxide layer over a conducting layer of silicon to expose said silicon layer in said contact holes, depositing a layer of platinum in said contact holes, and reacting said platinum layer with said exposed silicon to form a layer of platinum silicide in said contact holes, an improvement comprising reacting said platinum layer with said exposed silicon in an atmosphere of nitrogen and hydrogen whereby a layer of platinum silicide with a minimal amount of oxygen is present.
Claim 7
Dependent Claim
52 words
The improvement of claim 4 further comprising removing any unreacted platinum layer with aqua regia and wherein said platinum layer reacting step further comprises concluding said reacting step in an oxygen atmosphere whereby a protective layer of oxide is formed over said platinum silicide layer for said unreacted platinum layer removing step.
Claim 8
Dependent Claim
28 words
The improvement of claim 4 further comprising removing any unreacted platinum layer with aqua regia and water whereby selectivity of said aqua regia towards unreacted platinum is enhanced.
Claim 9
Independent Claim
170 words
A method of fabricating antifuses and contacts in an integrated circuit, comprising forming a layer of silicon dioxide over a conducting layer of silicon; forming contact holes in said silicon dioxide layer to expose portions of said silicon layer; depositing a contact metal layer in said contact holes and over said silicon dioxide layer; depositing a barrier metal layer over said contact metal layer; annealing said silicon layer portions with said contact metal layer in said contact holes; defining said contact metal and barrier metal layers to cover said contact holes; depositing a layer of amorphous silicon; defining said amorphous silicon layer so that portions of said amorphous silicon layer cover said contact holes where antifuses are to be located; depositing a layer of TiW; depositing a layer of aluminum alloy; and defining said layers of TiW and aluminum alloy into conducting lines to form antifuses in said contact holes covered by said amorphous silicon layer portions and contacts in said contact holes not covered by said amorphous silicon layer.
Claim 10
Independent Claim
170 words
A method of fabricating antifuses and contacts in an integrated circuit, comprising forming a layer of silicon dioxide over a conducting layer of silicon; forming contact holes in said silicon dioxide layer to expose portions of said silicon layer; depositing a contact metal layer in said contact holes and over said silicon dioxide layer; depositing a barrier metal layer over said contact metal layer; annealing said silicon layer portions with said contact metal layer in said contact holes; defining said contact metal and barrier metal layers to cover said contact holes; depositing a layer of amorphous silicon; defining said amorphous silicon layer so that portions of said amorphous silicon layer cover said contact holes where antifuses are to be located; depositing a layer of TiW; depositing a layer of aluminum alloy; and defining said layers of TiW and aluminum alloy into conducting lines to form antifuses in said contact holes covered by said amorphous silicon layer portions and contacts in said contact holes not covered by said amorphous silicon layer.
Claim 11
Dependent Claim
14 words
The method of claim 7 wherein said annealing step is a rapid thermal anneal.
Claim 12
Dependent Claim
28 words
The method of claim 8 wherein said rapid thermal anneal is performed at a temperature in the range of 500-800 degrees Centigrade for a period of 10-60 seconds.
Claim 13
Dependent Claim
12 words
The method of claim 7 wherein said contact metal layer comprises titanium.
Claim 14
Dependent Claim
13 words
The method of claim 10 wherein said barrier metal layer comprises titanium nitride.
Claim 15
Dependent Claim
12 words
The method of claim 10 wherein said barrier metal layer comprises TiW.
Claim 16
Dependent Claim
28 words
The method of claim 7 wherein said amorphous silicon layer depositing step is performed by plasma-enhanced chemical vapor deposition at a temperature in the range of 300°-400° C.
Claim 17
Independent Claim
236 words
A method of fabricating antifuses and contacts in an integrated circuit, comprising forming a layer of silicon dioxide over a conducting layer of silicon; forming contact holes in said silicon dioxide layer to expose portions of said silicon layer; forming relatively thin silicon oxide layers in said contact holes over said silicon layer portions; removing said relatively thin silicon oxide layers in said contact holes in which antifuses are to be located and not removing said relatively thin silicon oxide layers in said contact holes where contacts are to be located; depositing a contact metal layer in said contact holes and over silicon dioxide layer; reacting said contact metal layer with said silicon layer portions to form metal silicide layers in said contact holes in which antifuses are to be located; removing unreacted portions of said contact metal layer; depositing a layer of amorphous silicon; defining said amorphous silicon layer so that portions of said amorphous silicon layer cover said contact holes where antifuses are to be located; removing said relatively thin silicon oxide layers in said contact holes in which contacts are to be located; depositing a layer of TiW; depositing a layer of aluminum alloy; and defining said layers of TiW and aluminum alloy into conducting lines to form antifuses in said contact holes covered by said amorphous silicon layer portions and contacts in said contact holes not covered by said amorphous silicon layer.
Claim 18
Independent Claim
236 words
A method of fabricating antifuses and contacts in an integrated circuit, comprising forming a layer of silicon dioxide over a conducting layer of silicon; forming contact holes in said silicon dioxide layer to expose portions of said silicon layer; forming relatively thin silicon oxide layers in said contact holes over said silicon layer portions; removing said relatively thin silicon oxide layers in said contact holes in which antifuses are to be located and not removing said relatively thin silicon oxide layers in said contact holes where contacts are to be located; depositing a contact metal layer in said contact holes and over silicon dioxide layer; reacting said contact metal layer with said silicon layer portions to form metal silicide layers in said contact holes in which antifuses are to be located; removing unreacted portions of said contact metal layer; depositing a layer of amorphous silicon; defining said amorphous silicon layer so that portions of said amorphous silicon layer cover said contact holes where antifuses are to be located; removing said relatively thin silicon oxide layers in said contact holes in which contacts are to be located; depositing a layer of TiW; depositing a layer of aluminum alloy; and defining said layers of TiW and aluminum alloy into conducting lines to form antifuses in said contact holes covered by said amorphous silicon layer portions and contacts in said contact holes not covered by said amorphous silicon layer.
Claim 19
Dependent Claim
14 words
The method of claim 14 wherein said contact metal layer comprises a refractory metal.
Claim 20
Dependent Claim
11 words
The method of claim 15 wherein said refractory metal is titanium.
Claim 21
Dependent Claim
23 words
The method of claim 14 wherein said contact metal layer is selected from the group consisting of titanium, tantalum, tungsten, molybdenum and cobalt.
Claim 22
Dependent Claim
14 words
The method of claim 14 wherein said reacting step comprises a rapid thermal anneal.
Claim 23
Dependent Claim
28 words
The method of claim 18 wherein said rapid thermal anneal is performed at a temperature in the range of 500-800 degrees Centigrade for a period of 10-60 seconds.
Claim 24
Dependent Claim
25 words
The method of claim 14 further comprising the step of reflowing said silicon dioxide layer so that edges formed by said contact holes are rounded.
Claim 25
Dependent Claim
29 words
The method of claim 14 wherein said amorphous silicon layer depositing step is performed by plasma-enhanced chemical vapor deposition at a temperature in the range of 300°-400 ° C.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-18 | 1999-12-18 | 2000-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-18 | 2003-12-18 | 2004-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-18 | 2007-12-18 | 2008-06-18 | $7700.00 | Window Closed / Lapsed |