Interconnection arrangements for testing microelectronic circuit chips on a wafer

Claim 1

In a circuit configuration for use in testing microelectronic circuit chips, said circuit configuration being of the type comprising a flat wafer having non-adjacent opposite physical edges and thereon within the region bounded by said physical edges oo, said wafer surface having thereon an array of microelectronic circuit chips to be tested, each of the chips on said wafer comprising a digital circuit which processes digital information and to transfer digital information and control signals from a set of input connections on the chip to one of a plurality of sets of output connections on the chip selected by a switching circuit within the digital circuit, each set of output connections being connected to input connections of an adjacent chip on said wafer in accordance with the operation of the switching circuit thereby to set up a chain of interconnected sound chips in said array or said surface on said wafer which extends from a selected sound first chip and which bypasses faulty chips on said wafer, the improvement wherein said circuit configuration includes electrical connections which directly connect an output connection of each chip immediately adjacent a first physical edge of the said flat wafer to the input connection of a different chip adjacent a second physical edge of the said flat wafer whereby all chips behave electrically as though the surface of said flat wafer were unbounded in a direction transverse to said first and second edges and whereby the said selected first chip in said chain of interconnected chips is located immediately adjacent one of the physical edges of said flat wafer.