US4758985A
Expired / Lapsed
US
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Microprocessor oriented configurable logic element
Assignee: Xilinx Inc
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Filing: 1986-03-28
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Granted: 1988-07-19
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Expires: 2006-03-28
Abstract
Abstract A microprocessor controlled configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, a configurable status buffer, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip-flop with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output from among the output signals of the combinational logic element and the storage circuit. The configurable status buffer may be configured to provide status information on selected important internal signals of the configurable logic circuit. A microprocessor interface structure may access an array of these configurable logic circuits through the status buffer to read different internal output signals from different circuits in the array. Providing separate input and output to a microprocessor leaves the storage element free for other uses and does not require the logic provided by the logic elements.
Inventors
- 👤 William S. Carter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:43
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G11C19/282; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K5/00; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
182 words
A configurable logic element comprising: means for receiving a first plurality of N binary input signals; means for receiving a second plurality of M binary feedback signals; means for selecting K of said M+N binary signals (where K≦M+N); configurable combinational logic means for receiving said K binary signals from said means for selecting, said configurable combinational logic means having a plurality of configurations for generating selected binary output signals; a first configurable storage circuit for receiving selected ones of said binary output signals of said configurable combinational logic means and selected ones of said N binary input signals and for generating said M binary feedback signals, said configurable storage circuit having a plurality of configurations; a configurable select logic comprising means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic; and means for reading the status of a selected one of said output signals of said combinational logic means and said M feedback signals.
Claim 2
Dependent Claim
182 words
A configurable logic element comprising: means for receiving a first plurality of N binary input signals; means for receiving a second plurality of M binary feedback signals; means for selecting K of said M+N binary signals (where K≦M+N); configurable combinational logic means for receiving said K binary signals from said means for selecting, said configurable combinational logic means having a plurality of configurations for generating selected binary output signals; a first configurable storage circuit for receiving selected ones of said binary output signals of said configurable combinational logic means and selected ones of said N binary input signals and for generating said M binary feedback signals, said configurable storage circuit having a plurality of configurations; a configurable select logic comprising means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic; and means for reading the status of a selected one of said output signals of said combinational logic means and said M feedback signals.
Claim 3
Dependent Claim
82 words
A configurable logic element as in claim 1 further including: a second storage circuit for storing a data signal and for providing an output signal representing said stored data signal; and configurable means for receiving said output signal of said second storage circuit and providing said output signal of said second storage circuit to said means for receiving a first plurality of N binary input signals, said output signal of said second storage circuit being one of said N binary input signals.
Claim 4
Dependent Claim
31 words
A configurable logic element as in claim 2 wherein said means for reading the status further includes means for reading the status of said output signal of said second storage circuit.
Claim 5
Dependent Claim
98 words
A configurable logic element as in claim 1 wherein said means for reading the status comprises: a configurable switch for receiving said output signals of said combinational logic circuit and said M binary feedback signals, said configurable switch having a plurality of configurations, said configurable switch providing in each configuration a signal representing a different one of the signals received by said configurable switch; and a three-state buffer for receiving the signal provided by said configurable storage circuit and for providing an output signal representing the signal received by said three-state buffer when said three-state buffer is enabled.
Claim 6
Dependent Claim
205 words
A configurable logic element comprising: means for receiving a first plurality of N binary input signals; means for receiving a second plurality of M binary feedback signals; means for selecting K of said M+N binary signals (where K≦M+N); configurable combinational logic means for receiving said K binary signals from said means for selecting, said configurable combinational logic means having a plurality of configurations for generating selected binary output signals; a first configurable storage circuit for receiving selected ones of said binary output signals of said configurable combinational logic means and selected ones of said N binary input signals and for generating said M binary feedback signals, said configurable storage circuit having a plurality of configurations; a configurable select logic comprising means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic; a second storage circuit for storing a storage data signal and for providing an output signal representing said storage data signal; and configurable means for providing said output signal of said second storage circuit to said means for receiving a first plurality of N binary input signals.
Claim 7
Dependent Claim
205 words
A configurable logic element comprising: means for receiving a first plurality of N binary input signals; means for receiving a second plurality of M binary feedback signals; means for selecting K of said M+N binary signals (where K≦M+N); configurable combinational logic means for receiving said K binary signals from said means for selecting, said configurable combinational logic means having a plurality of configurations for generating selected binary output signals; a first configurable storage circuit for receiving selected ones of said binary output signals of said configurable combinational logic means and selected ones of said N binary input signals and for generating said M binary feedback signals, said configurable storage circuit having a plurality of configurations; a configurable select logic comprising means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic; a second storage circuit for storing a storage data signal and for providing an output signal representing said storage data signal; and configurable means for providing said output signal of said second storage circuit to said means for receiving a first plurality of N binary input signals.
Claim 8
Dependent Claim
40 words
A configurable logic array comprising: a plurality of configurable logic elements, each of said configurable logic elements being as in claim 5; and means for selectively communicating data signals from a data bus to each of said second storage circuits.
Claim 9
Dependent Claim
48 words
A configurable logic array as in claim 6 wherein said means for selectively communicating data signals includes a microprocessor interface circuit for receiving address signals and control signals from said microprocessor and for generating write signals which determine which of said second storage elements store a data signal.
Claim 10
Dependent Claim
25 words
A configurable logic array as in claim 7 wherein said plurality of configurable logic elements are arranged in a rectangular configuration of rows and columns.
Claim 11
Dependent Claim
54 words
A configurable logic array comprising: a plurality of configurable logic elements each of said configurable logic elements being as in claim 1; and means for selecting particular ones of said means for reading the status and for providing the signal read by said particular ones of said means for reading to a data bus.
Claim 12
Dependent Claim
18 words
A configurable logic array as in claim 9 wherein said means for selecting includes a computer interface logic.
Claim 13
Dependent Claim
70 words
A configurable logic array comprising: a plurality of configurable logic elements, each of said logic elements being as in claim 2, a buffer having a first state for receiving a selected signal read by one of said means for reading the status and for providing said selected signal to a microprocessor, and a second state for providing a data signal from said microprocessor to one of said second storage circuits.
References Cited (Backward Citations)
US3967251A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-19 | 1992-01-18 | 1992-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-19 | 1996-01-18 | 1996-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-19 | 2000-01-18 | 2000-07-19 | $7700.00 | Window Closed / Lapsed |