User variable computer memory module

Claim 2

In a digital computer comprising a central processing unit (CPU) and memory connected by backplane wiring, a memory module which can be reconfigured for various memory size and word length applications by rewiring said backplane, comprising: addressable memory devices arranged in rows and columns, address line amplifiers for receiving addressing information from said CPU and for driving the address input lines of said memory devices, a pulse driver coupled to said CPU for each row of memory devices for enabling said row of memory devices to store or output signal information bits, a read/write amplifier for each column of memory devices for coupling one bit of information between said CPU and said memory devices in each column, a printed circuit board for mounting said memory devices, said address line amplifiers, said pulse drivers and said read/write amplifiers, and wherein said backplane wiring is individually coupled to each of said read/write amplifiers for ORing the input/output lines of said read/write amplifiers and for selectively enabling all of said read/write amplifiers or any subset thereof, to configure said memory module to a particular memory size and word length.

Claim 3

The apparatus of claim 1 wherein a plurality of said memory modules are coupled in parallel to extend the effective length of each row, thereby increasing the word size of said computer memory.

Claim 4

The apertures of claim 1 wherein a plurality of said memory modules are coupled in parallel to extend the effective depth of each column, thereby increasing the memory size of said computer memory.

Claim 5

The apparatus of claim 3 further comprising switching means for supplying electrical power to the read/write amplifiers of the one module of said plurality that is currently being written into or read from.

Claim 6

In a digital computer comprising a central processing unit and memory connected by backplane wiring, a memory module which can be reconfigured for various memory size and word length applications by rewiring said backplane comprising: a plurality of addressable memory devices arranged in m rows of n columns, each memory device having P address line inputs and storing 2 P bits, P address line amplifiers for driving the address input lines of all of said memory devices, m pulse drivers, each one for enabling the reading into or writing out from said memory devices in any one row of said memory device, n read/write amplifiers, one for each column of said memory devices for supplying to or for receiving from all of said memory devices in said column one bit of each memory module output word, a printed circuit board on which said memory devices, said address line amplifier, said pulse drivers and said read/write amplifiers are mounted, and wherein said backplane wiring is individually coupled to each of said read/write amplifiers for selectively ORing the input/output lines of subsets of said read/write amplifiers and for enabling one read/write amplifier in each of said subsets to configure said memory module to store 2 P mn bit words, 2 P mn one bit words, or variations therebetween, the total bit size of said memory module not to exceed 2 P mn bits.

Claim 7

In a digital computer comprising a central processing unit and memory connected by backplane wiring, a memory module which can be reconfigured for various memory size and word length applications by rewiring said backplane comprising: a plurality of addressable memory devices arranged in m rows of n columns, each memory device having P address line inputs and storing 2 P bits, P address line amplifiers for driving the address input lines of all of said memory devices, m pulse drivers, each one for enabling the reading into or writing out from said memory devices in any one row of said memory device, n read/write amplifiers, one for each column of said memory devices for supplying to or for receiving from all of said memory devices in said column one bit of each memory module output word, a printed circuit board on which said memory devices, said address line amplifier, said pulse drivers and said read/write amplifiers are mounted, and wherein said backplane wiring is individually coupled to each of said read/write amplifiers for selectively ORing the input/output lines of subsets of said read/write amplifiers and for enabling one read/write amplifier in each of said subsets to configure said memory module to store 2 P mn bit words, 2 P mn one bit words, or variations therebetween, the total bit size of said memory module not to exceed 2 P mn bits.

Claim 8

In a computer comprising a central processing unit (CPU) and memory connected by backplane wiring, the method of configuring a memory module comprising rows and columns of addressable memory devices into any one of several variations of memory size and word length by providing a standard memory module and rewiring the backpanel comprising the steps of: arranging addressable memory devices onto said memory module in rows and columns wherein the number of rows multiplied by the number of locations per memory device represents the maximum number of words that the module may contain and the number of columns represents the maximum number of bits the output word may contain, addressing all memory devices through the backplane wiring, enabling the input/output of all devices in any one row of memory devices by providing an enabling signal through the backplane wiring, transmitting the inputs/outputs of all memory devices in each column to a read/write amplifier located on said memory module, connecting together into subsets those wires in the backplane which couple the CPU to the read/write amplifiers, and enabling one of each subset of read/write amplifiers by providing a read/write enabling signal through the backplane wiring so that one bit of binary information may be transmitted between the CPU and one location of one memory device for each subset of columns.

Claim 9

In a computer comprising a central processing unit (CPU) and memory connected by backplane wiring, the method of configuring a memory module comprising rows and columns of addressable memory devices into any one of several variations of memory size and word length by providing a standard memory module and rewiring the backpanel comprising the steps of: arranging addressable memory devices onto said memory module in rows and columns wherein the number of rows multiplied by the number of locations per memory device represents the maximum number of words that the module may contain and the number of columns represents the maximum number of bits the output word may contain, addressing all memory devices through the backplane wiring, enabling the input/output of all devices in any one row of memory devices by providing an enabling signal through the backplane wiring, transmitting the inputs/outputs of all memory devices in each column to a read/write amplifier located on said memory module, connecting together into subsets those wires in the backplane which couple the CPU to the read/write amplifiers, and enabling one of each subset of read/write amplifiers by providing a read/write enabling signal through the backplane wiring so that one bit of binary information may be transmitted between the CPU and one location of one memory device for each subset of columns.

Claim 10

The method of claim 6 including the step of connecting an extension module identical to said memory module in parallel to said memory module to increase the word length.

Claim 11

The method of claim 6 including the step of adding an extension module identical to said memory module and accessing either said extension module or said memory module to increase the memory size of said memory.

Claim 12

The method of claim 8 including the step of disconnecting the power to the read/write amplifiers of the nodule not currently being accessed to conserve power.