US3750111A
Expired / Lapsed
US
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Modular digital detector circuit arrangement
Assignee: AG Communication Systems Corp
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Filing: 1972-08-23
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Granted: 1973-07-31
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Expires: 1992-08-23
Abstract
Abstract A multi-stage digital detector logic circuit arrangement is provided utilizing a plurality of cascaded read-only memory ROM arrays of the transistor-transistor logic configuration to detect m addresses out of N total input information addresses, where m is a quantity less than N. Each read-only memory array has n input addresses where n is a quantity less than N but greater than m, and provides digital output addresses corresponding to logic conditions of zero true addresses, less than m true addresses, exactly m true addresses, and greater than m true addresses. The greater than m true addresses are processed by OR logic gates to a final result and the other logic conditions are processed through cascaded ROM arrays until a final ROM array provides a final logic result of zero true addresses out of N addresses, m true addresses out of N addresses, and NOT m out of N total addresses.
Inventors
- 👤 S Pitroda
- 👤 A Kobylar
- 👤 R Lindsay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:30
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/085; H; H03; H03M; H03M13/00; H03M13/47; H03M13/51
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
466 words
A digital detector circuit arrangement for use with a digital information system for detecting the occurrence of a first quantity of logic input addresses out of a total quantity of logic input addresses comprising: a plurality of digital memory circuit means, each thereof having a second quantity of logic input addresses greater than said first quantity thereof and less than said total quantity of logic input addresses, and further having a first quantity of logic output addresses equal to one greater than said first quantity of input addresses, said output addresses including a sequential series of selectively occurring output addresses varying from one logic input address out of said second quantity of input addresses to said first quantity of input addresses out of said second quantity thereof and further incLuding one output address representative of greater than said first quantity of input addresses out of said second quantity thereof, said plurality of memory circuit means being arranged in multiple adjacent arrays of independent connected ones of said memory circuit means within a given array and including a first array, a plurality of intermediate arrays and a final array, the number of memory circuit means in each following adjacent array decreasing by a concentration factor defined by said first quantity of input addresses divided by said second quantity thereof, the number of said memory circuit means in said first array being the next highest order integer of said total quantity of input addresses divided by said second quantity thereof, the number of said memory circuit means in any selected intermediate array of said multiple arrays being the next highest order integer of the number of said memory circuit means for said immediately preceding one of said arrays multiplied by said concentration factor, and a final of said arrays including a single one of said memory circuit means, digital decoding means in selected ones of said multiple adjacent arrays for receiving multiple ones of said one output address and providing therefrom a single one of said one output address whereby all such single ones of said one output addresses are combined to following adjacent arrays until a final single one of said one output addresses is provided, and decision logic circuit means for receiving said first quantity of logic output addresses from said memory circuit means of said final array and said final single one of said one output addresses from said digital decoding means and providing therefrom final digital logic output addresses including a logic output address representing said first quantity of input addresses out of said total quantity thereof, another logic output address representing zero input addresses out of said total quantity thereof and still another output address representing other than said zero and said first quantity of input addresses out of said total quantity thereof.
Claim 2
Dependent Claim
466 words
A digital detector circuit arrangement for use with a digital information system for detecting the occurrence of a first quantity of logic input addresses out of a total quantity of logic input addresses comprising: a plurality of digital memory circuit means, each thereof having a second quantity of logic input addresses greater than said first quantity thereof and less than said total quantity of logic input addresses, and further having a first quantity of logic output addresses equal to one greater than said first quantity of input addresses, said output addresses including a sequential series of selectively occurring output addresses varying from one logic input address out of said second quantity of input addresses to said first quantity of input addresses out of said second quantity thereof and further incLuding one output address representative of greater than said first quantity of input addresses out of said second quantity thereof, said plurality of memory circuit means being arranged in multiple adjacent arrays of independent connected ones of said memory circuit means within a given array and including a first array, a plurality of intermediate arrays and a final array, the number of memory circuit means in each following adjacent array decreasing by a concentration factor defined by said first quantity of input addresses divided by said second quantity thereof, the number of said memory circuit means in said first array being the next highest order integer of said total quantity of input addresses divided by said second quantity thereof, the number of said memory circuit means in any selected intermediate array of said multiple arrays being the next highest order integer of the number of said memory circuit means for said immediately preceding one of said arrays multiplied by said concentration factor, and a final of said arrays including a single one of said memory circuit means, digital decoding means in selected ones of said multiple adjacent arrays for receiving multiple ones of said one output address and providing therefrom a single one of said one output address whereby all such single ones of said one output addresses are combined to following adjacent arrays until a final single one of said one output addresses is provided, and decision logic circuit means for receiving said first quantity of logic output addresses from said memory circuit means of said final array and said final single one of said one output addresses from said digital decoding means and providing therefrom final digital logic output addresses including a logic output address representing said first quantity of input addresses out of said total quantity thereof, another logic output address representing zero input addresses out of said total quantity thereof and still another output address representing other than said zero and said first quantity of input addresses out of said total quantity thereof.
Claim 3
Dependent Claim
22 words
The digital detector circuit arrangement of claim 1 wherein said digital memory circuit means are comprised of read-only memory transistor-transistor logic circuits.
Claim 4
Dependent Claim
178 words
The digital detector circuit arrangement of claim 2 wherein said first quantity of input addresses is equal to one true logic input address out of said total logic input addresses, said plurality of read-only memory circuits is represented by a plurality of additive terms, each term being equal to the next highest order integer of said total quantity of logic input addresses divided by said second quantity thereof raised to an exponential power equal to the successive number of said term and said term being added so long as said total quantity of input addresses is greater than said second quantity thereof raised to an exponential power of one less than the successive number of said term, the number of input addresses to be processed by said arrays is equal to said second quantity raised to an exponential power corresponding to the number of said arrays, and said first quantity of output addresses is represented by one out of said second quantity of input addresses and greater than said one out of said second quantity of input addresses.
Claim 5
Dependent Claim
19 words
The digital detector circuit arrangement of claim 1 wherein said digital decoding means are comprised of logic OR gates.
Claim 6
Dependent Claim
292 words
A digital detector circuit arrangement for a digital information system for detecting the occurrence of m logic addresses out of N total logic a:dresses comprising: a plurality of digital memory circuit means having n logic input addresses and m+1 logic output addresses, respectively, where m is less than n and n is less than N, said m+1 logic output addresses being 1 out of n through m out of n inclusive and greater than m out of n, said plurality of memorY circuit means being arranged in multiple adjacent arrays of decreasing numbers of said memory circuit means with a concentration factor between said adjacent arrays of m divided by n, the number of said memory circuit means in a first of said adjacent arrays being the next highest order integer of N divided by n and in each intermediate one of said adjacent arrays being the next highest order integer of the number of said memory circuit means in an immediately preceding one of said adjacent arrays multiplied by said concentration factor, and a final of said adjacent arrays including a single one of said memory circuit means, digital decoding means in selected ones of said arrays for receiving multiple ones of the greater than m out of n logic addresses and providing therefrom a single one of said greater than m out of n output addresses to subsequent arrays, and decision logic circuit means for receiving from said final array the greater than m out of n output address and the one out of n through the m out of n output addresses and providing therefrom a final plurality of digital logic output addresses comprising m out of N, zero inputs out of N, and NOT m out of N.
Claim 7
Dependent Claim
292 words
A digital detector circuit arrangement for a digital information system for detecting the occurrence of m logic addresses out of N total logic a:dresses comprising: a plurality of digital memory circuit means having n logic input addresses and m+1 logic output addresses, respectively, where m is less than n and n is less than N, said m+1 logic output addresses being 1 out of n through m out of n inclusive and greater than m out of n, said plurality of memorY circuit means being arranged in multiple adjacent arrays of decreasing numbers of said memory circuit means with a concentration factor between said adjacent arrays of m divided by n, the number of said memory circuit means in a first of said adjacent arrays being the next highest order integer of N divided by n and in each intermediate one of said adjacent arrays being the next highest order integer of the number of said memory circuit means in an immediately preceding one of said adjacent arrays multiplied by said concentration factor, and a final of said adjacent arrays including a single one of said memory circuit means, digital decoding means in selected ones of said arrays for receiving multiple ones of the greater than m out of n logic addresses and providing therefrom a single one of said greater than m out of n output addresses to subsequent arrays, and decision logic circuit means for receiving from said final array the greater than m out of n output address and the one out of n through the m out of n output addresses and providing therefrom a final plurality of digital logic output addresses comprising m out of N, zero inputs out of N, and NOT m out of N.
Claim 8
Dependent Claim
23 words
The digital detector circuit arrangement of claim 5 wherein said digital memory circuit means have a total binary bit capacity of 2n. (m+1).
Claim 9
Dependent Claim
341 words
A digital detector circuit arrangement for detecting the occurrence of a single true binary input address out of a total quantity of binary input addresses, comprising: a plurality of digital memory circuit means arranged in multiple adjacent stages, each of said memory circuit means having a first quantity of input addresses thereto greater than one and at least a pair of output addresses therefrom, one of said pair of output addresses defined by a logic condition of one out of said first quantity of input addresses and another of said pair of output addresses defined by another logic condition of greater than one out of said first quantity thereof, the number of such input addresses to be processed by said stages being defined by said first quantity of input addresses raised to an exponential power corresponding to the number of said stages, said plurality of digital memory circuit means being represented by a plurality of additive terms, each term being equal to the next highest order integer of said total quantity of logic input addresses divided by said first quantity thereof raised to an exponential power equal to the successive number of said term and said term being added so long as said total quantity of input addresses is greater than said first quantity thereof raised to an exponential power of one less than the successive number of said term, means for receiving and decoding a plurality of said other output addresses to obtain a single one of said other output addresses, and decision logic circuit means for receiving a final one of said one output address from said memory circuit means and a final one of said other output address from said decoding means and providing therefrom final digital logic output addresses including a first logic condition of one out of said total quantity of logic input addresses, a second logic output address representing zero input addresses out of said total quantity thereof and a third output address representing greater than one out of said total quantity of input addresses.
Claim 10
Dependent Claim
341 words
A digital detector circuit arrangement for detecting the occurrence of a single true binary input address out of a total quantity of binary input addresses, comprising: a plurality of digital memory circuit means arranged in multiple adjacent stages, each of said memory circuit means having a first quantity of input addresses thereto greater than one and at least a pair of output addresses therefrom, one of said pair of output addresses defined by a logic condition of one out of said first quantity of input addresses and another of said pair of output addresses defined by another logic condition of greater than one out of said first quantity thereof, the number of such input addresses to be processed by said stages being defined by said first quantity of input addresses raised to an exponential power corresponding to the number of said stages, said plurality of digital memory circuit means being represented by a plurality of additive terms, each term being equal to the next highest order integer of said total quantity of logic input addresses divided by said first quantity thereof raised to an exponential power equal to the successive number of said term and said term being added so long as said total quantity of input addresses is greater than said first quantity thereof raised to an exponential power of one less than the successive number of said term, means for receiving and decoding a plurality of said other output addresses to obtain a single one of said other output addresses, and decision logic circuit means for receiving a final one of said one output address from said memory circuit means and a final one of said other output address from said decoding means and providing therefrom final digital logic output addresses including a first logic condition of one out of said total quantity of logic input addresses, a second logic output address representing zero input addresses out of said total quantity thereof and a third output address representing greater than one out of said total quantity of input addresses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |