US3594730A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Information processing system including multiple function translators
Assignee: AT&T Inc
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Filing: 1968-06-07
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Granted: 1971-07-20
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Expires: 1988-06-07
Abstract
Abstract An information processing system characterized by modularity of design and good maintenance features includes a plurality of oneout-of-N translators each of which includes double-output detection circuitry. Some of the translators are operated in a conventional manner to convert a multidigit input word into energization of one particular one of N output lines emanating therefrom. Others of the translators are supplied with periodic clock signals, steady-state reference signals and instruction signals. In response to such a set of signals, these other translators are operated in a unique manner to provide a specified plurality of sequential control signals which are applied to a matrix array to cause the readout therefrom of a corresponding plurality of stored words.
Inventors
- 👤 Wing N Toy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:57
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F11/00; G06F11/07; G06F11/08; G06F11/085
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
91 words
In combination in an information processing system, a plurality of one-out-of-N translators each including a plurality of output lines, means for applying successive instruction signals to said translators, and means for applying periodic clock signals and steady-state reference signals to said translators, each of said translators including means responsive to said applied signals for generating and respectively applying to specified ones of the output lines thereof a plurality of sequential control signals during the time in which a single instruction signal of said successive instruction signals is applied to the translator.
Claim 2
Dependent Claim
91 words
In combination in an information processing system, a plurality of one-out-of-N translators each including a plurality of output lines, means for applying successive instruction signals to said translators, and means for applying periodic clock signals and steady-state reference signals to said translators, each of said translators including means responsive to said applied signals for generating and respectively applying to specified ones of the output lines thereof a plurality of sequential control signals during the time in which a single instruction signal of said successive instruction signals is applied to the translator.
Claim 3
Dependent Claim
33 words
A combination as in claim 1 further including a matrix array connected to said output lines to provide a multidigit output word from the array in response to each control signal applied thereto.
Claim 4
Dependent Claim
26 words
A combination as in claim 2 wherein each of said translators includes error control circuitry for detecting the generation by said translator of simultaneous control signals.
Claim 5
Dependent Claim
52 words
A combination as in claim 3 further including an additional plurality of one-out-of-N translators each including a plurality of output lines, each of said additional translators being responsive to a portion of each output word provided by said matrix array for applying a control signal to one of the output lines thereof.
Claim 6
Dependent Claim
20 words
A combination as in claim 4 further including means for sequentially enabling selected ones of the additional plurality of translators.
Claim 7
Dependent Claim
23 words
A combination as in claim 5 further including data and logic circuits connected to the output lines of said additional plurality of translators.
Claim 8
Dependent Claim
34 words
A combination as in claim 6 further including means for applying to at least one of said first-mentioned plurality of translators conditional signals indicative of information representations contained in said data and logic circuits.
Claim 9
Dependent Claim
83 words
A multiple function translator comprising a plurality of cross-point units, means responsive to an input binary code word for selecting a particular one of said units, means for applying steady-state signals and timing signals to said selecting means, and means for applying each of successive instruction signals simultaneously to respective selected sets of plural units whereby the respective units of each set in turn are controlled to provide sequential output signals in response to each different one of said successively applied instruction signals.
Claim 10
Dependent Claim
83 words
A multiple function translator comprising a plurality of cross-point units, means responsive to an input binary code word for selecting a particular one of said units, means for applying steady-state signals and timing signals to said selecting means, and means for applying each of successive instruction signals simultaneously to respective selected sets of plural units whereby the respective units of each set in turn are controlled to provide sequential output signals in response to each different one of said successively applied instruction signals.
Claim 11
Dependent Claim
93 words
In combination in a translator, first and second pretranslators each including a plurality of lines emanating therefrom, each of the lines from said first pretranslator being disposed in an orthogonal relationship with respect to each of the lines from said second pretranslator thereby to define a multiplicity of intersections, a multiplicity of cross-point units respectively connected to the lines defining each of said intersections, means for applyiNg periodic clock and steady-state reference signals to said first and second pretranslators, and means for applying instruction signals directly to selected ones of said cross-point units.
Claim 12
Dependent Claim
93 words
In combination in a translator, first and second pretranslators each including a plurality of lines emanating therefrom, each of the lines from said first pretranslator being disposed in an orthogonal relationship with respect to each of the lines from said second pretranslator thereby to define a multiplicity of intersections, a multiplicity of cross-point units respectively connected to the lines defining each of said intersections, means for applyiNg periodic clock and steady-state reference signals to said first and second pretranslators, and means for applying instruction signals directly to selected ones of said cross-point units.
Claim 13
Dependent Claim
20 words
A combination as in claim 9 further including means for applying conditional logic signals directly to said selected cross-point units.
Claim 14
Dependent Claim
24 words
A combination as in claim 10 further including error control circuitry connected to said cross-point units for detecting the occurrence of double outputs therefrom.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-19 | 1975-01-18 | 1975-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-19 | 1979-01-18 | 1979-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-19 | 1983-01-18 | 1983-07-20 | $7700.00 | Window Closed / Lapsed |