Capacitive read only memory

Claim 2

In a capacitive read only memory including a matrix having a plurality of word paths and sense paths selectively capacitively coupled together, the improvement of circuit means for inverted operation of said capacitive read only memory for providing the logical product of input signals comprising: input means electrically coupled to said word paths and dividing each such path into a true and a complement signal line, means for delivering input pulses to the true signal lines and inverting such input pulses on said complement signal lines, a double input terminal AND gate in each true and complement signal line and receiving each input pulse on one of its two input terminals, means for pulsing all of the sense paths except a desired sense path, said pulsing means including means for applying a strobe pulse for each input pulse to the other of said input terminals of said AND gates for enabling the same, and output means for logically inverting the signals on all sense paths and thereby providing an output signal on said desired sense path for indicating the logical product of said input pulses.

Claim 3

In a capacitive read only memory according to claim 1 wherein each said sense path has a register for storing an output signal conveyed by its respective sense path, each such register being normally in a first logical state but being responsive to an output signal on its respective sense path for switching to a second logical state.

Claim 4

In a capacitive read only memory according to claim 2 wherein each such register has a second logical state output and wherein a second matrix of electrically coupled word paths and sense paths has its word paths respectively electrically connected to the second logical state outputs of said registers.

Claim 5

A capacitive read only memory comprising: a matrix having a plurality of sense lines selectively capacitively coupled to predetermined word lines wherein an enabling signal on one of said word lines is coupled to selected ones of said sense lines, logic means electrically coupled to said word lines of said matrix and dividing said word lines into a plurality of sets each having two lines where one line of each of said sets is electrically connected through inversion means to said other line whereby the electrical signal on said one line is a complement of the electrical signal on said other line, a plurality of buffer registers operatively and electrically coupled respectively to each one of said sense lines of said matrix, said registers being normally in a first logical state and responsive to a signal on its respective sense line for switching its associated buffer register from said first state to a second logical state, means for applying an electrical strobe pulse to all of said sense lines except those sense lines receiving an enabling signal from one of said word lines, and means for logically inverting the signals on said sense lines with the result that only those buffer registers associated with the sense lines which bear signals after said inversion takes place are switched to said second logical state.

Claim 6

A capacitive read only memory comprising: a matrix having a plurality of sense lines selectively capacitively coupled to predetermined word lines wherein an enabling signal on one of said word lines is coupled to selected ones of said sense lines, logic means electrically coupled to said word lines of said matrix and dividing said word lines into a plurality of sets each having two lines where one line of each of said sets is electrically connected through inversion means to said other line whereby the electrical signal on said one line is a complement of the electrical signal on said other line, a plurality of buffer registers operatively and electrically coupled respectively to each one of said sense lines of said matrix, said registers being normally in a first logical state and responsive to a signal on its respective sense line for switching its associated buffer register from said first state to a second logical state, means for applying an electrical strobe pulse to all of said sense lines except those sense lines receiving an enabling signal from one of said word lines, and means for logically inverting the signals on said sense lines with the result that only those buffer registers associated with the sense lines which bear signals after said inversion takes place are switched to said second logical state.

Claim 7

A composable read only memory comprising: a first matrix having a plurality of sense lines selectively capacitively coupled to predetermined word lines wherein an enabling signal on one of said word lines is coupled to selected ones of said sense lines, a plurality of buffer registers operatively and electrically coupled respectively to each one of said sense lines, said registers normally in one logical state and responsive to a signal from said first matrix for switching said buffer register from said normal state to a switched logical state, a second matrix having a plurality of word lines each electrically coupled to the switched logical state output of each of said buffer registers wherein an enabling signal from said switched logical state of said buffer registers is coupled to selected ones of said word lines of said second matrix, logic means electrically coupled to said word lines of said first matrix for dividing said word lines into a plurality of sets wherein an electrical signal applied to said logic means for one of said sets will energize only one word line in said set for enabling said first matrix and will deenergize all other word lines of said set, and whereby said first matrix is a product generator performing a logical AND function.

Claim 8

A composable read only memory comprising: a first matrix having a plurality of sense lines selectively capacitively coupled to predetermined word lines wherein an enabling signal on one of said word lines is coupled to selected ones of said sense lines, a plurality of buffer registers operatively and electrically coupled respectively to each one of said sense lines, said registers normally in one logical state and responsive to a signal from said first matrix for switching said buffer register from said normal state to a switched logical state, a second matrix having a plurality of word lines each electrically coupled to the switched logical state output of each of said buffer registers wherein an enabling signal from said switched logical state of said buffer registers is coupled to selected ones of said word lines of said second matrix, logic means electrically coupled to said word lines of said first matrix for dividing said word lines into a plurality of sets wherein an electrical signal applied to said logic means for one of said sets will energize only one word line in said set for enabling said first matrix and will deenergize all other word lines of said set, and whereby said first matrix is a product generator performing a logical AND function.

Claim 9

A composable read only memory according to claim 5 additionally including a plurality of buffer registers operatively and electrically coupled respectively to each of said sense lines of said second matrix said registers normally in one logical state and responsive to a signal outputted from said second matrix on said sense lines for switching said buffer from said normal state to a switch logical state.

Claim 10

A composable read only memory according to claim 5 wherein said logic means divides said word lines into a plurality of sets having two lines each where one line of each of said sets is electrically connected through an inversion means to said other line whereby the electrical signal on said one line is a complement of the electrical signal on said other line.