US3786436A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory expansion arrangement in a central processor
Assignee: AG Communication Systems Corp
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Filing: 1973-03-14
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Granted: 1974-01-15
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Expires: 1993-03-14
Abstract
Abstract A page register in the central processor comprises 3N bistable devices, N each for an instruction field, a branch field, and a data field, to extend addresses by N bits beyond the capacity of the operand portion of the format of instructions. A ''''load page register'''' instruction uses the operand to designate load the branch field and/or the data field, or transfer the instruction field to the data field; and also supplies the values for loading the branch and/or data field. A ''''last page reference'''' register is also provided to which the instruction and data fields are transferred from the page register during execution of each instruction, while the address in a program counter is transferred to a ''''last program count'''' register, to be stored in memory when a ''''branch and store program'''' linkage instruction is executed.
Inventors
- 👤 P Zelinski
- 👤 L Jones
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:11
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
242 words
A meMory expansion arrangement in a computer central processor of a digital computing system which comprises said processor and a memory, said processor comprising a plurality of registers, an arithmetic logic unit, control logic and an address bus; wherein said registers include a program counter, an instruction register, and a page register which is part of the memory expansion arrangement; wherein the information stored in the memory includes instruction words and data words, an instruction set having a format comprising given bit positions for an operation code, and M given bit position for an operand which for some instructions is an address; means to supply an instruction address from the program counter and the page register via the address bus to the memory to read the instruction word and place it in the instruction register; wherein said page register comprises N bistable devices for an instruction field, N bistable devices for a branch field and N bistable devices for a data field; one of the instructions of the set being a ''''load page register'''' instructions in which the operand has some bit positions which designate which field or fields of the page register to load or to transfer from one field to another, and other bit positions of the operand comprise information to be loaded; and means responsive to the ''''load page register'''' instruction in the instruction register to load or transfer information in the page register in accordance with the instruction.
Claim 2
Dependent Claim
242 words
A meMory expansion arrangement in a computer central processor of a digital computing system which comprises said processor and a memory, said processor comprising a plurality of registers, an arithmetic logic unit, control logic and an address bus; wherein said registers include a program counter, an instruction register, and a page register which is part of the memory expansion arrangement; wherein the information stored in the memory includes instruction words and data words, an instruction set having a format comprising given bit positions for an operation code, and M given bit position for an operand which for some instructions is an address; means to supply an instruction address from the program counter and the page register via the address bus to the memory to read the instruction word and place it in the instruction register; wherein said page register comprises N bistable devices for an instruction field, N bistable devices for a branch field and N bistable devices for a data field; one of the instructions of the set being a ''''load page register'''' instructions in which the operand has some bit positions which designate which field or fields of the page register to load or to transfer from one field to another, and other bit positions of the operand comprise information to be loaded; and means responsive to the ''''load page register'''' instruction in the instruction register to load or transfer information in the page register in accordance with the instruction.
Claim 3
Dependent Claim
149 words
A memory expansion arrangement according to claim 1, further including a ''''last page reference'''' register comprising N bistable devices for an instruction field and N bistable devices for a data field, with coupling gates from outputs of the page register instruction and data field devices to respective inputs of the instruction and data field devices of the ''''last page reference'''' register; wherein the computer central processor further includes a ''''last program count'''' register having inputs connected via coupling gates to respective outputs of the program counter; means effective during the execution of each instruction to enable said coupling gates to transfer the address information in the program counter and page registers to the ''''last program count'''' and ''''last page reference'''' registers; and means responsive to a ''''branch and store program'''' instruction to store the address information from the ''''last program count'''' and ''''last page reference'''' registers into the memmory.
Claim 4
Dependent Claim
151 words
A memory expansion arrangement according to claim 1, wherein the format of the ''''load page register'''' instruction extends the operation code by using a group of bit positions of the operand with respective codes for ''''load data field,'''' ''''load branch field,'''' ''''load data and branch field,'''' and ''''transfer instruction field to data field;'''' and other bit positions for data field and branch field data; and wherein said means responsive to the ''''load page register'''' instruction in the instruction register comprises gating means coupling the data field and branch field bit position from the instruction register via a data bus to respective inputs of the data and branch field devices of the page register, and outputs of the instruction field devices to inputs of the data field devices; and logic means with inputs from the instruction register to enable the gating means to load the page register in accordance with the instruction.
Claim 5
Dependent Claim
83 words
A memory expansion arrangement according to claim 3, wherein for branch instructions the control logic includes means to supply a ''''load program counter'''' signal which is effective to enable gate means to load an effective address corresponding to the operand of the branch instruction into the program counter; and wherein there are gate means coupling the output of the branch field devices to inputs of the instruction field devices, and The last said gate means is enabled by the ''''load program counter'''' signal.
Claim 6
Dependent Claim
42 words
A memory expansion arrangement according to claim 4, including gate means coupling outputs of the page register branch field to the address bus, and means to enable the last said gate means during the execution of a ''''branch and store program'''' instruction.
Claim 7
Dependent Claim
146 words
A memory expansion arrangement according to claim 4 wherein said instruction set format further includes a bit position for an indirect address bit which causes a word for address modification to be read from the operand location, and indirect address paging bistable device with means to set it responsive to the indirect address bit being true in the instruction register and to reset it responsive to the program counter becoming an address source; means responsive to branch return instructions in which the indirect address paging bistable device is set to load address information from the word read from the operand location via another register, with 2N bit positions beyond the low order M bit positions into the page register, N bits into the branch field devices and other N bits into the data field devices; the low order M bits being loaded into the program counter.
Claim 8
Dependent Claim
42 words
A memory expansion arrangement according to claim 6, in which the branch return instructions include a return instruction and a branch return reset instruction which are both unconditional branch instructions, and the latter said instruction causes reset of the highest active interrupt.
Claim 9
Dependent Claim
139 words
A memory expansion arrangement according to claim 6, further including a ''''last page reference'''' register comprising N bistable devices for an instruction field and N bistable devices for a data field, with coupling gates from outputs of the page register instruction and data field devices of the ''''last page reference'''' register; wherein the computer central processor further includes a ''''last program count'''' register having inputs connected via coupling gates to respective outputs of the program counter; means effective during the execution of each instruction to enable said coupling gates to transfer the address information in the program counter and page register to the ''''last program count'''' and ''''last page reference'''' registers; and means responsive to a ''''branch and store program'''' instruction to store the address information from the ''''last program count'''' and ''''last page reference'''' registers into the memory.
Claim 10
Dependent Claim
171 words
A memory expansion arrangement according to claim 8, wherein means responsive to the indirect address bit in the instruction register being true with the branch and store program instruction inhibits gating page address bits to the address bus to thereby provide an address reference to page zero, means responsive to the indirect address paging bistable device being set with the branch and store program instruction to gate information from the word at the operand location via said another register to the branch field devices of the page register, means effective with the indirect address bit no longer true in the instruction register with the branch and store program instruction to gate the information from the branch field of the page register to the address bus, while the M low order bits of the word read from the operand location are also gated to the address bus, to thereby provide the address of the location where the information from the ''''last program count'''' and ''''last page reference'''' registers is to be stored.
Claim 11
Dependent Claim
52 words
A memory expansion arrangement according to claim 9, wherein means effective after storage of the ''''last program count'''' and ''''last page reference'''' information enables a load program counter signal, which enables gate means coupling the output of the branch field devices to inputs of the instruction field devices of the page register.
Claim 12
Dependent Claim
88 words
A memory expansion arrangement according to claim 10, whereiN means responsive to certain branch instructions with the indirect address bit true, when the program counter is enabled as an address source, cause the page instruction field output of the page register to be gated to the address bus; and means responsive to instructions other than said certain branch instructions or the branch and store program instruction, with the indirect address bit true, to gate the outputs of the data field of the page register to the address bus.
Claim 13
Dependent Claim
29 words
An address modification arrangement according to claim 11, wherein said certain branch instructions comprise a branch return reset, a return, a branch unconditionally, and a branch then halt instruction.
References Cited (Backward Citations)
US3533075A
Cited
US3657705A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-14 | 1977-07-16 | 1978-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-14 | 1981-07-16 | 1982-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-14 | 1985-07-16 | 1986-01-15 | $7700.00 | Window Closed / Lapsed |