Reduced-area, read-only memory

Claim 3

An improved integraged-circuit, read-only memory, including programmable read-only memory, having a plurality of parallel word lines, a plurality of parallel bit lines, the bit lines being perpendicular to the word lines, each bit and word line being selectable by its own line-driving transistor, the word line-driving transistors being driven by word address lines as expanded by a word decoder, and the bit line-driving transistors being driven by bit address lines as expanded by a bit decoder, wherein the improvement comprises; a. a word decoder driven by one less than all of the word address lines, each word decoder output driving two adjacent word line-driving transistors; b. two auxiliary bit lines driven by the true and complement of the word address line that is not driving the word decoder; c. circuitry means located at the crossover of each of the word lines and the appropriate auxiliary bit line, and connected between the lines to selectively suppress, according to the logical state of the auxiliary bit lines, the selection of one word line of each pair of word lines that is driven by a single word decoder output; d. a bit decoder driven by one less than all of the bit address lines, each bit decoder output driving two adjacent bit line-driving transistors; e. two auxiliary word lines driven by the true and complement of the bit address line that is not driving the bit decoder; and f. circuitry means located at the crossover of each of the bit lines and the appropriate auxiliary word line, and connected between the lines the selectively suppress, according to the logical state of the auxiliary word lines, the selection of one bit line of each pair of bit lines that is driven by a single bit decoder output.

Claim 4

An improved integraged-circuit, read-only memory, including programmable read-only memory, having a plurality of parallel word lines, a plurality of parallel bit lines, the bit lines being perpendicular to the word lines, each bit and word line being selectable by its own line-driving transistor, the word line-driving transistors being driven by word address lines as expanded by a word decoder, and the bit line-driving transistors being driven by bit address lines as expanded by a bit decoder, wherein the improvement comprises; a. a word decoder driven by one less than all of the word address lines, each word decoder output driving two adjacent word line-driving transistors; b. two auxiliary bit lines driven by the true and complement of the word address line that is not driving the word decoder; c. circuitry means located at the crossover of each of the word lines and the appropriate auxiliary bit line, and connected between the lines to selectively suppress, according to the logical state of the auxiliary bit lines, the selection of one word line of each pair of word lines that is driven by a single word decoder output; d. a bit decoder driven by one less than all of the bit address lines, each bit decoder output driving two adjacent bit line-driving transistors; e. two auxiliary word lines driven by the true and complement of the bit address line that is not driving the bit decoder; and f. circuitry means located at the crossover of each of the bit lines and the appropriate auxiliary word line, and connected between the lines the selectively suppress, according to the logical state of the auxiliary word lines, the selection of one bit line of each pair of bit lines that is driven by a single bit decoder output.

Claim 5

A read-only memory according to claim 2 wherein said circuitry means is a diode.

Claim 6

A read-only memory according to claim 3 wherein said diode is a Schottky diode.

Claim 7

An integrated-circuit, read-only memory, including programmable read-only memory, fabricated in and on a semiconductor substrate, the memory comprising; a. a plurality of parallel word lines; b. a plurality of parallel bit lines, the bit lines being perpendicular to the word lines; c. memory cells located at the crossover of each word line and each bit line; d. a plurality of first circuitry means, each connected between the word line and the bit line of a memory cell indicating a binary information state, the cells without said semiconductor means indicating the other binary information state; e. a word line-driving transistor for selecting and driving each word line; f. input, word address lines; g. a word decoder driven by one less than all of the word address lines, each word decoder output driving two adjacent word line-driving transistors; h. two auxiliary bit lines driven by the true and complement of the word address line that is not driving the word decoder; i. a plurality of second circuitry means connected between every word line and its appropriate auxiliary bit line to selectively suppress, according to the logical state of the auxiliary bit lines, the selection of one word line of each pair of word lines that is driven by a single word decorder output; j. a bit line-driving transistor for selecting and driving each bit line; k. input, bit address lines; l. a bit decoder driven by one less than all of the bit address lines, each bit decoder output driving two adjacent bit line-driving transistors; m. two auxiliary word lines driven by the true and complement of th bit address line that is not driving the bit decoder; and n. a plurality of said second circuitry means connected between every bit line and its appropriate auxiliary word line to selectively suppress, according to the logical state of the auxiliary word lines, the selection of one bit line of each pair of bit lines that is driven by a single bit decoder output.

Claim 8

An integrated-circuit, read-only memory, including programmable read-only memory, fabricated in and on a semiconductor substrate, the memory comprising; a. a plurality of parallel word lines; b. a plurality of parallel bit lines, the bit lines being perpendicular to the word lines; c. memory cells located at the crossover of each word line and each bit line; d. a plurality of first circuitry means, each connected between the word line and the bit line of a memory cell indicating a binary information state, the cells without said semiconductor means indicating the other binary information state; e. a word line-driving transistor for selecting and driving each word line; f. input, word address lines; g. a word decoder driven by one less than all of the word address lines, each word decoder output driving two adjacent word line-driving transistors; h. two auxiliary bit lines driven by the true and complement of the word address line that is not driving the word decoder; i. a plurality of second circuitry means connected between every word line and its appropriate auxiliary bit line to selectively suppress, according to the logical state of the auxiliary bit lines, the selection of one word line of each pair of word lines that is driven by a single word decorder output; j. a bit line-driving transistor for selecting and driving each bit line; k. input, bit address lines; l. a bit decoder driven by one less than all of the bit address lines, each bit decoder output driving two adjacent bit line-driving transistors; m. two auxiliary word lines driven by the true and complement of th bit address line that is not driving the bit decoder; and n. a plurality of said second circuitry means connected between every bit line and its appropriate auxiliary word line to selectively suppress, according to the logical state of the auxiliary word lines, the selection of one bit line of each pair of bit lines that is driven by a single bit decoder output.

Claim 9

A read-only memory according to claim 5 wherein both said first and said second circuitry means are diodes.

Claim 10

A read-only memory according to claim 6 further comprising an insulating layer between the semiconductor substrate and said diodes.

Claim 11

A read-only memory according to claim 7 wherein said diodes are Schottky diodes.

Claim 12

A read-only memory according to claim 5 wherein said first circuitry means is a voltage-programmable resistor in series with a Schottky diode.

Claim 13

A read-only memory according to claim 9 wherein said second circuitry means is a Schottky diode.