Memory system wherein individual bits may be updated

Claim 2

A memory system, comprising: a first memory for storing data words having a plurality of bits and capable of being accessed only for one entire data word at a time; a second memory for storing at least some of the data words stored in said first memory; means for accessing a data word from said second memory and including means for changing the value of at least one bit of the accessed data word, said means for changing comprising: a first multiplexer for receiving groups of new bits from a plurality of sources and selecting one of the groups of new bits in response to a control input; and a second multiplexer for receiving the selected group of new bits from said first multiplexer and the data word having the bit to be changed from said second memory and exchanging one bit in the selected group of new bits from said first multiplexer with the bit to be changed in the data word from said second memory; and means for returning the accessed data word, including the at least one changed bit, to both said first memory and said second memory.

Claim 3

A memory system, comprising: a first memory providing the data output of said memory system and being word addressable, said first memory having a size of nxm, where m is the number of words stored in said first memory and n is the number of bits in each word; a second memory having a size of nxm and storing duplicates of the words stored in said first memory; and bit changing circuitry for changing individual bits of the words stored in said first and second memory, comprising a first multiplexer for receiving and selecting among several sources of groups of new bits, and a second multiplexer for receiving the selected group of new bits from said first multiplexer and a word having at least one bit to be changed from said second memory, said second multiplexer for exchanging the bit to be changed with one of the new bits and for providing the word having the changed bit for storage back in both said first memory and said second memory.

Claim 4

A memory system, comprising: a first memory providing the data output of said memory system and being word addressable, said first memory having a size of nxm, where m is the number of words stored in said first memory and n is the number of bits in each word; a second memory having a size of nxm and storing duplicates of the words stored in said first memory; and bit changing circuitry for changing individual bits of the words stored in said first and second memory, comprising a first multiplexer for receiving and selecting among several sources of groups of new bits, and a second multiplexer for receiving the selected group of new bits from said first multiplexer and a word having at least one bit to be changed from said second memory, said second multiplexer for exchanging the bit to be changed with one of the new bits and for providing the word having the changed bit for storage back in both said first memory and said second memory.

Claim 5

In a data processing system having a processor and a parity memory within said processor, the improvement wherein said parity memory comprises: a primary parity memory having data inputs and a plurality of memory locations, each memory location for storing a plurality of parity bits, said primary parity memory capable of being accessed only for the entire plurality of parity bits in each memory location at a time; a copy parity memory having data inputs and a plurality of memory locations corresponding to the memory locations in said primary memory and for storing the same pluralities of parity bits that are stored in said primary parity memory; bit changing circuitry for receiving the parity bits within one memory location of said copy parity memory, for receiving a new bit having a value to which one of the parity bits from said copy parity memory is to be changed, and for changing the one of the parity bits to the value of the new bit, said bit changing circuitry comprising: a first multiplexer connected for receiving and selecting among groups of new bits coming from a plurality of sources; and a second multiplexer connected for receiving a selected group of new bits from said first multiplexer and the parity bits, including the one of the parity bits to be changed, from said copy parity memory, and for exchanging the one of the parity bits from said copy parity memory with one of the new bits from said first multiplexer; and means for connecting said bit changing circuitry to the data inputs of both said copy parity memory and said primary parity memory so that the parity bits from the bit changing circuitry, including the changed bit, are returned to their corresponding memory locations in both said copy parity memory and said primary parity memory.

Claim 6

In a data processing system having a processor and a parity memory within said processor, the improvement wherein said parity memory comprises: a primary parity memory having data inputs and a plurality of memory locations, each memory location for storing a plurality of parity bits, said primary parity memory capable of being accessed only for the entire plurality of parity bits in each memory location at a time; a copy parity memory having data inputs and a plurality of memory locations corresponding to the memory locations in said primary memory and for storing the same pluralities of parity bits that are stored in said primary parity memory; bit changing circuitry for receiving the parity bits within one memory location of said copy parity memory, for receiving a new bit having a value to which one of the parity bits from said copy parity memory is to be changed, and for changing the one of the parity bits to the value of the new bit, said bit changing circuitry comprising: a first multiplexer connected for receiving and selecting among groups of new bits coming from a plurality of sources; and a second multiplexer connected for receiving a selected group of new bits from said first multiplexer and the parity bits, including the one of the parity bits to be changed, from said copy parity memory, and for exchanging the one of the parity bits from said copy parity memory with one of the new bits from said first multiplexer; and means for connecting said bit changing circuitry to the data inputs of both said copy parity memory and said primary parity memory so that the parity bits from the bit changing circuitry, including the changed bit, are returned to their corresponding memory locations in both said copy parity memory and said primary parity memory.

Claim 7

In a data processing system having a processor and a parity memory within said processor, the improvement wherein said parity memory comprises: a primary parity memory having data inputs and a plurality of memory locations, each memory location for storing a plurality of parity bits, said primary parity memory capable of being accessed only for the entire plurality of parity bits in each memory location at a time; a copy parity memory having data inputs and a plurality of memory locations corresponding to the memory locations in said primary memory and for storing the same pluralities of parity bits that are stored in said primary parity memory; bit changing circuitry for receiving the parity bits within one memory location of said copy parity memory, for receiving a new bit having a value to which one of the parity bits from said copy parity memory is to be changed, and for changing the one of the parity bits to the value of the new bit, said bit changing circuitry comprising: a first multiplexer for receiving the parity bits within one memory location of said copy parity memory and groups of new bits from one or more first sources that provide the new bits at a fast speed in relation to said processor, and for selecting either the parity bits or one of the groups of new bits; and a second multiplexer receiving the selected bits from said first multiplexer and groups of new bits from one or more second sources that provide the new bits at a slow speed in relation to said first sources, and for exchanging one of the bits from said second sources with one of the bits from said first multiplexer; and means for connecting said bit changing circuitry to the data inputs of both said copy parity memory and said primary parity memory so that the parity bits from the bit changing circuitry, including the changed bit, are returned to their corresponding memory locations in both said copy parity memory and said primary parity memory.

Claim 8

In a data processing system having a processor and a parity memory within said processor, the improvement wherein said parity memory comprises: a primary parity memory having data inputs and a plurality of memory locations, each memory location for storing a plurality of parity bits, said primary parity memory capable of being accessed only for the entire plurality of parity bits in each memory location at a time; a copy parity memory having data inputs and a plurality of memory locations corresponding to the memory locations in said primary memory and for storing the same pluralities of parity bits that are stored in said primary parity memory; bit changing circuitry for receiving the parity bits within one memory location of said copy parity memory, for receiving a new bit having a value to which one of the parity bits from said copy parity memory is to be changed, and for changing the one of the parity bits to the value of the new bit, said bit changing circuitry comprising: a first multiplexer for receiving the parity bits within one memory location of said copy parity memory and groups of new bits from one or more first sources that provide the new bits at a fast speed in relation to said processor, and for selecting either the parity bits or one of the groups of new bits; and a second multiplexer receiving the selected bits from said first multiplexer and groups of new bits from one or more second sources that provide the new bits at a slow speed in relation to said first sources, and for exchanging one of the bits from said second sources with one of the bits from said first multiplexer; and means for connecting said bit changing circuitry to the data inputs of both said copy parity memory and said primary parity memory so that the parity bits from the bit changing circuitry, including the changed bit, are returned to their corresponding memory locations in both said copy parity memory and said primary parity memory.