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US3755791A Expired / Lapsed US ⏱️ 0.0 years remaining

Memory system with temporary or permanent substitution of cells for defective cells

Assignee: International Business Machines Corp
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Filing: 1972-06-01
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Granted: 1973-08-28
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Expires: 1992-06-01
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Abstract

Abstract A memory storage system comprising both a main memory array and an alternate storage memory array coupled by a circuit that can either semipermanently or reversibly substitute the alternate array for a portion of the main array and retain the alternate array in its substituted position even when the memory is in a power down condition. The described circuit achieves this by utilizing nonvolatile semiconductor devices arranged in a cross coupled configuration that can, if desired, be made to either temporarily or semipermanently substitute the alternate array for any desired portion of the main array.

Inventors

  • 👤 L Arzubi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 13:27
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/789

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 175 words
A memory storage system comprising: a memory storage array containing storage locations, a memory address register for selecting a storage location in said memory storage array, input signal means for providing an input signal to said array, said array comprising a plurality of functionally isolated individual storage locations electrically interconnected into a main storage group and a redundant storage line a circuit coupled to the main storage group and to the redundant storage line said circuit having a first state for directing an input signal from said input signal means to a selected storage location in said main storage group and a second state for redirecting the input signal from the selected storage location in said main storage group to the redundant storage line whenever the main storage group to which the circuit is coupled contains a defective storage location, and biasing means coupled to said circuit for setting said circuit in one of said states, said circuit containing non-volatile, variable threshold devices that can be set to turn on at a selected input voltage.
Claim 2
Dependent Claim 175 words
A memory storage system comprising: a memory storage array containing storage locations, a memory address register for selecting a storage location in said memory storage array, input signal means for providing an input signal to said array, said array comprising a plurality of functionally isolated individual storage locations electrically interconnected into a main storage group and a redundant storage line a circuit coupled to the main storage group and to the redundant storage line said circuit having a first state for directing an input signal from said input signal means to a selected storage location in said main storage group and a second state for redirecting the input signal from the selected storage location in said main storage group to the redundant storage line whenever the main storage group to which the circuit is coupled contains a defective storage location, and biasing means coupled to said circuit for setting said circuit in one of said states, said circuit containing non-volatile, variable threshold devices that can be set to turn on at a selected input voltage.
Claim 3
Dependent Claim 44 words
The system of claim 1 wherein there is further provided first means for applying a first voltage to said circuit for setting the threshold of one of said non-volatile, variable threshold devices to cause said circuit to be latched into one of said states.
Claim 4
Dependent Claim 42 words
The system of claim 2 wherein there is further provided second means for applying a second voltage to said circuit for unlatching said circuit from the state in which it is set and relatching said circuit in the other of said states.
Claim 5
Dependent Claim 35 words
The system of claim 2 wherein said main storage group is divided into a plurality of portions and each portion has a circuit coupled thereto which circuit is also coupled to said redundant storage line.
Claim 6
Dependent Claim 86 words
A memory system comprising a memory storage array containing main storage and alternate storage locations, input signal means for providing an input signal to said array, switching means having a first output coupled to said main storage locations, a second output coupled to said alternate storage locations and an input coupled to said input signal means, and control means coupled to said switching means for controlling said switching means to selectively switch the input signal from one of said outputs to the other of said outputs.
Claim 7
Dependent Claim 86 words
A memory system comprising a memory storage array containing main storage and alternate storage locations, input signal means for providing an input signal to said array, switching means having a first output coupled to said main storage locations, a second output coupled to said alternate storage locations and an input coupled to said input signal means, and control means coupled to said switching means for controlling said switching means to selectively switch the input signal from one of said outputs to the other of said outputs.
Claim 8
Dependent Claim 20 words
The system of claim 5 wherein said control means includes a circuit having a first state and a second state.
Claim 9
Dependent Claim 22 words
The system of claim 6 wherein said circuit includes non-volatile devices that can semipermanently latch the circuit in one of said states.
Claim 10
Dependent Claim 55 words
The system of claim 7 wherein said control means further includes means for applying a first voltage condition to said circuit for setting said circuit into one of said states and for applying a second voltage condition to said non-volatile devices to semipermanently latch the circuit into the state in which it has been set.
Claim 11
Dependent Claim 12 words
The system of claim 7 wherein said non-volatile devices comprise metal-nitride-oxide semiconductors.

References Cited (Backward Citations)

US3245049A Cited
US3331058A Cited
US3422402A Cited
US3432812A Cited
US3560764A Cited
US3588830A Cited
US3585607A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-08-27 1977-02-26 1977-08-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-08-27 1981-02-26 1981-08-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-08-27 1985-02-26 1985-08-28 $7700.00 Window Closed / Lapsed

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