US3560764A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse-powered data storage cell
Assignee: International Business Machines Corp
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Filing: 1970-03-02
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Granted: 1971-02-02
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Expires: 1990-03-02
Abstract
Abstract This specification describes semiconductor storage cells for use in monolithic memories that perform storage and/or associative storage functions. These cells each comprise a pair of semiconductor devices which are coupled together to form a bistable circuit. The loads for the bistable circuits are other semiconductor devices which can be biased to regulate current drawn by the bistable circuit from a source for powering the bistable circuit. These current-regulating semiconductor devices are gated on and off to intermittently power the bistable circuit. During the periods in which power is gated-off, the bistable circuit is maintained in the proper operating state by charge stored in the elements of the bistable circuit.
Inventors
- 👤 Joseph J Mcdowell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:29
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402; G11C11/4023; G11C11/41; G11C11/412; G11C11/413; G11C11/417; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
244 words
In a storage cell having a pair of cross-coupled semiconductor devices with internal capacitance connected through a load to a source of power so as to form a bistable circuit which with one of said semiconductor devices biased conductive and the other of said semiconductor devices biased substantially nonconductive stores a bit of data, the improvement which comprises: a. a first semiconductor load device having two terminals connected in series with the source of power and said one semiconductor device and having a third control terminal for regulating the current between the other two terminals of the first semiconductor load device; b. a second semiconductor load device having two terminals connected in series with the source of power and said other semiconductor device and having a third control terminal for regulating the current between the other two terminals of the second semiconductor load device; and c. pulse means coupled to said control terminals of said first and second semiconductor load devices to normally maintain said current turned off to reduce the power supplied through the load devices to the cross-coupled semiconductor devices below the level necessary to retain a bit of data stored in the bistable circuit while charge stored in said internal capacitance maintains said one cross-coupled semiconductor device biased conductive and said other cross-coupled semiconductor device biased substantially nonconductive and for periodically rendering said current on to charge said internal capacitances at intervals sufficiently short to prevent the loss of stored data.
Claim 2
Dependent Claim
244 words
In a storage cell having a pair of cross-coupled semiconductor devices with internal capacitance connected through a load to a source of power so as to form a bistable circuit which with one of said semiconductor devices biased conductive and the other of said semiconductor devices biased substantially nonconductive stores a bit of data, the improvement which comprises: a. a first semiconductor load device having two terminals connected in series with the source of power and said one semiconductor device and having a third control terminal for regulating the current between the other two terminals of the first semiconductor load device; b. a second semiconductor load device having two terminals connected in series with the source of power and said other semiconductor device and having a third control terminal for regulating the current between the other two terminals of the second semiconductor load device; and c. pulse means coupled to said control terminals of said first and second semiconductor load devices to normally maintain said current turned off to reduce the power supplied through the load devices to the cross-coupled semiconductor devices below the level necessary to retain a bit of data stored in the bistable circuit while charge stored in said internal capacitance maintains said one cross-coupled semiconductor device biased conductive and said other cross-coupled semiconductor device biased substantially nonconductive and for periodically rendering said current on to charge said internal capacitances at intervals sufficiently short to prevent the loss of stored data.
Claim 3
Dependent Claim
22 words
The storage cell of claim 1 wherein said cross-coupled semiconductor devices and said first and second load devices are metal oxide semiconductors.
Claim 4
Dependent Claim
154 words
The storage cell of claim 1 including: a. a first additional semiconductor load device in shunt with the first of said semiconductor load device, said first additional semiconductor load device having a control terminal which can be biased to render the first additional semiconductor load device conductive and nonconductive; b. a second additional semiconductor load device in shunt with the second of said semiconductor load device, said second additional semiconductor load device having a control terminal which can be biased to render the second additional semiconductor load device conductive and nonconductive; c. differential sense means in series with the first and second additional semiconductor load devices for sensing the state of the storage cell when the first and second additional semiconductor devices are biased conductive whereby the information in the storage cell can be sensed without destroying the information stored in the cell when the first and second load transistors are biased on nonconducting.
Claim 5
Dependent Claim
22 words
The storage cell of claim 3 wherein said cross-coupled semiconductor devices and said first and second load devices are metal oxide semiconductors.
Claim 6
Dependent Claim
162 words
In a storage cell having a pair of cross-coupled semiconductor devices with internal capacitances to store a bit of information when one of the semiconductor devices is biased conductive and the other of tHe semiconductor devices is biased nonconductive, the improvement which comprises: a. input-output semiconductor means coupling said pair of semiconductor devices to bit lines for the transmission of current between the bit lines and said pair of semiconductor devices for the purpose of reading and writing the information stored in the storage cell, said input-output semiconductor means normally being biased nonconductive while charge stored in said internal capacitance maintains said one semiconductor device biased conductive and said other semiconductor device biased nonconductive but being rendered conductive to read the data stored in said storage cell; and b. biasing means coupled through the bit lines to the input-output semiconductor means for supplying charge to charge the internal capacitance through the input-output semiconductor devices while said input-output semiconductor devices are rendered conductive.
Claim 7
Dependent Claim
162 words
In a storage cell having a pair of cross-coupled semiconductor devices with internal capacitances to store a bit of information when one of the semiconductor devices is biased conductive and the other of tHe semiconductor devices is biased nonconductive, the improvement which comprises: a. input-output semiconductor means coupling said pair of semiconductor devices to bit lines for the transmission of current between the bit lines and said pair of semiconductor devices for the purpose of reading and writing the information stored in the storage cell, said input-output semiconductor means normally being biased nonconductive while charge stored in said internal capacitance maintains said one semiconductor device biased conductive and said other semiconductor device biased nonconductive but being rendered conductive to read the data stored in said storage cell; and b. biasing means coupled through the bit lines to the input-output semiconductor means for supplying charge to charge the internal capacitance through the input-output semiconductor devices while said input-output semiconductor devices are rendered conductive.
Claim 8
Dependent Claim
24 words
The storage cell of claim 5 wherein said pair of semiconductor devices are cross-coupled FET devices and said input-output semiconductor devices are FET devices.
Claim 9
Dependent Claim
201 words
In a storage cell having a pair of semiconductor devices with internal capacitances to store a bit of information when one of the semiconductor devices is biased conductive and the other of the semiconductor devices is biased nonconductive, the improvement which comprises: a. input-output semiconductor means coupling said pair of semiconductor devices to bit lines for the transmission of current between the bit lines and said pair of semiconductor devices for the purpose of reading and writing the information stored in the storage cell, said input-output semiconductor means normally being biased nonconductive while charge stored in said internal capacitance maintains said one semiconductor device biased conductive and said other semiconductor device biased nonconductive but being rendered conductive to read the data stored in said storage cell; b. word address pulse source means coupled to the input-output semiconductor means for rendering said input-output semiconductor means conductive to read the data stored in said cell; and c. biasing means coupled through the bit lines to the input-output semiconductor means for supplying charge to charge the internal capacitances through the input-output semiconductor devices only while said input-output semiconductor devices are rendered conductive by read pulses continually supplied by said word address pulse source means.
Claim 10
Dependent Claim
201 words
In a storage cell having a pair of semiconductor devices with internal capacitances to store a bit of information when one of the semiconductor devices is biased conductive and the other of the semiconductor devices is biased nonconductive, the improvement which comprises: a. input-output semiconductor means coupling said pair of semiconductor devices to bit lines for the transmission of current between the bit lines and said pair of semiconductor devices for the purpose of reading and writing the information stored in the storage cell, said input-output semiconductor means normally being biased nonconductive while charge stored in said internal capacitance maintains said one semiconductor device biased conductive and said other semiconductor device biased nonconductive but being rendered conductive to read the data stored in said storage cell; b. word address pulse source means coupled to the input-output semiconductor means for rendering said input-output semiconductor means conductive to read the data stored in said cell; and c. biasing means coupled through the bit lines to the input-output semiconductor means for supplying charge to charge the internal capacitances through the input-output semiconductor devices only while said input-output semiconductor devices are rendered conductive by read pulses continually supplied by said word address pulse source means.
Claim 11
Dependent Claim
36 words
The storage cell of claim 7 including semiconductor load devices for providing paths to charge the internal capacitances of the pair of semiconductor devices while the storage cell is not being addressed for reading or writing.
Claim 12
Dependent Claim
28 words
The storage cell of claim 8 wherein the semiconductor load devices are turned on and off to supply power to charge the internal capacitances on an intermittent basis.
Claim 13
Dependent Claim
22 words
The storage cell of claim 8 wherein the semiconductor load devices are turned on and off to associatively interrogate the storage cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-01 | 1974-08-03 | 1975-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-01 | 1978-08-03 | 1979-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-01 | 1982-08-03 | 1983-02-02 | $7700.00 | Window Closed / Lapsed |