US3668644A
Expired / Lapsed
US
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Failsafe memory system
Assignee: Unisys Corp
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Filing: 1970-02-09
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Granted: 1972-06-06
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Expires: 1990-02-09
Abstract
Abstract A memory system comprising a plurality of memories containing identical information stored at corresponding addresses. Information is requested simultaneously from the memories by a data processor. The requested information is simultaneously supplied to the inputs of a first OR-gate which operates to pass such requested information when it is supplied thereto from any or all of the memories. A plurality of first error detection means are associated with each memory, each operating to disable its associated memory from supplying requested information to the data processor when it detects an error in the information at the memory output, and each operating to send an error signal to the data processor informing it that an error has been detected. Second error detection means are associated with the first ORgate for detecting an error in the information at its output being sent to the data processor. A second OR-gate couples error signals to the data processor in a manner that a signal, indicating that an error has been detected somewhere in the system, will be supplied to the data processor upon receipt, by the second OR-gate, of an error signal from any or all of the first and second error detection means. Responsive to its receipt of such signal, the data processor is programmed to re-request the originally requested information simultaneously from the memories. Any disabled memory does not respond to such re-request until repaired, updated with information from the other memories, and re-enabled into the system.
Inventors
- 👤 Floyd W Looschen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:20
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/74; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1044
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
215 words
In an error checking redundant memory system comprising: multiple addressable memory modules, each with multiple memory locations, corresponding memory locations in each memory module having identical information units composed of binary coded bits stored therein and coded according to a preselected parity, the memory modules each having an output at which the bits of an information unit therefrom are presented simultaneously; and apparatus for reading out an information unit from corresponding memory locations in all memory modules and for detecting an error in parity comprising: means for addressing each of said memory modules selecting the corresponding memory locations in each memory module, means for enabling each of said memory modules to simultaneously read out an information unit from the addressed memory location, and simultaneously present the bits of the information unit at the corresponding output, an ''''OR'''' gating circuit for simultaneously ''''OR''''ing together the corresponding bits in the information units from the outputs of all memory modules to produce a single output information unit, a parity check circuit for each memory module for indicatIng an error in parity of an information unit from the corresponding memory module, and means responsive to an error indication from a parity check circuit for disabling the corresponding memory module from presenting further information units to the ''''OR'''' gating circuit.
Claim 2
Dependent Claim
215 words
In an error checking redundant memory system comprising: multiple addressable memory modules, each with multiple memory locations, corresponding memory locations in each memory module having identical information units composed of binary coded bits stored therein and coded according to a preselected parity, the memory modules each having an output at which the bits of an information unit therefrom are presented simultaneously; and apparatus for reading out an information unit from corresponding memory locations in all memory modules and for detecting an error in parity comprising: means for addressing each of said memory modules selecting the corresponding memory locations in each memory module, means for enabling each of said memory modules to simultaneously read out an information unit from the addressed memory location, and simultaneously present the bits of the information unit at the corresponding output, an ''''OR'''' gating circuit for simultaneously ''''OR''''ing together the corresponding bits in the information units from the outputs of all memory modules to produce a single output information unit, a parity check circuit for each memory module for indicatIng an error in parity of an information unit from the corresponding memory module, and means responsive to an error indication from a parity check circuit for disabling the corresponding memory module from presenting further information units to the ''''OR'''' gating circuit.
Claim 3
Dependent Claim
85 words
The system of claim 1 wherein the disabling means comprises a plurality of storage devices, each respectively associated with a different one of the plurality of parity check circuits, each said storage device responding to the detection of an error by the associated error check circuit for applying and maintaining a corresponding signal to the associated memory module, the associated memory module comprising control means responsive to the applied signal for disabling such memory module, from presenting further information units to the ''''OR'''' gating circuit.
Claim 4
Dependent Claim
27 words
A system according to claim 1 comprising a further parity check circuit for indicating an error in parity of an information unit from the ''''OR'''' gating circuit.
Claim 5
Dependent Claim
212 words
In a data processing system having an error checking redundant memory system, the data processing system comprising: multiple addressable memory modules, each with multiple memory locations, corresponding memory locations in each memory module having identical information units composed of binary coded bits stored therein and coded according to a preselected parity, the memory modules each having an output at which the bits of an information unit therefrom are presented simultaneously; a data processor comprising: means for addressing each of said memory modules selecting the corresponding memory locations in each memory module, and means for enabling each of said memory modules to simultaneously read out an information unit from the addressed memory location, and simultaneously present the bits of the information unit at the corresponding output; an ''''OR''''gating circuit for simultaneously ''''OR''''ing together the corresponding bits in the information units from the outputs of all memory modules for producing a single output information unit to said data processor; means for indicating an error in parity of one of said information units comprising a parity check circuit for each memory module for indicating an error in parity from the corresponding memory module; and means responsive to an indication from a parity check circuit for disabling the corresponding memory module from providing further information units.
Claim 6
Dependent Claim
212 words
In a data processing system having an error checking redundant memory system, the data processing system comprising: multiple addressable memory modules, each with multiple memory locations, corresponding memory locations in each memory module having identical information units composed of binary coded bits stored therein and coded according to a preselected parity, the memory modules each having an output at which the bits of an information unit therefrom are presented simultaneously; a data processor comprising: means for addressing each of said memory modules selecting the corresponding memory locations in each memory module, and means for enabling each of said memory modules to simultaneously read out an information unit from the addressed memory location, and simultaneously present the bits of the information unit at the corresponding output; an ''''OR''''gating circuit for simultaneously ''''OR''''ing together the corresponding bits in the information units from the outputs of all memory modules for producing a single output information unit to said data processor; means for indicating an error in parity of one of said information units comprising a parity check circuit for each memory module for indicating an error in parity from the corresponding memory module; and means responsive to an indication from a parity check circuit for disabling the corresponding memory module from providing further information units.
Claim 7
Dependent Claim
85 words
The system of claim 4 wherein the disabling means comprises a plurality of storage devices, each respectively associated with a different one of the plurality of parity check circuits, each said storage device responding to the detection of an error by the associated error check circuit for applying and maintaining a corresponding signal to the associated memory module, the associated memory module comprising control means responsive to the applied signal for disabling such memory module, from presenting further information units to the ''''OR'''' gating circuit.
Claim 8
Dependent Claim
27 words
A system according to claim 4 comprising a further parity check circuit for indicating an error in parity of an information unit from the ''''OR'''' gating circuit.
Claim 9
Dependent Claim
27 words
The system of claim 5 comprising means for coupling an indication of a parity error from any one of said parity check circuit to said data processor.
Claim 10
Dependent Claim
30 words
The system of claim 7 wherein said data processor is operative upon receipt of a parity error for readdressing and re-enabling each of said memory modules at the same address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |