Programmable, asynchronous logic cell and array

Claim 2

A digital logic cell comprising: a. a set of logic elements comprising disjunctive and conjunctive elements, each of the disjunctive and conjunctive elements having a first input, a second input, and an output; and b. a set of switches for programmably, operatively interconnecting the disjunctive and conjunctive elements neighboring each switch, each switch having (1) first and second signal inputs for connection to outputs of selected ones of the disjunctive and conjunctive elements and (2) at least one output for connection to an input of a selected one of the disjunctive and conjunctive elements.

Claim 3

The digital logic cell of claim 1 wherein the switches are operatively disposed in an alternating pattern with the logic elements.

Claim 4

The digital logic cell of claim 2 wherein each switch has first and second outputs, and for each switch, the first signal input thereof being connected to an output of a first logic element, the second signal input thereof being connected to an output of a second logic element, the first output thereof being connected to an input of a third logic element and the second output thereof being connected to an input of a fourth logic element.

Claim 5

The digital logic cell of claim 1 wherein an output of each switch is connected to an input of one of said disjunctive and conjunctive elements and the output of each of the disjunctive and conjunctive elements is connected to an input of one of said switches.

Claim 6

The digital logic cell of any of claims 1, 3 and 4 wherein the disjunctive elements comprise exclusive-OR gates, and, further, wherein the conjunctive elements comprise Muller C-elements.

Claim 7

The digital logic cell of claim 5 further including means for supplying to selected, predetermined inputs of the exclusive-OR gates, logical one and logical zero signals.

Claim 8

The digital logic cell of claim 6 wherein the set of switches includes the means for supplying the logical one and logical zero signals.

Claim 9

The digital logic cell of claim 6 wherein each switch further has a zero input for receiving a logical zero signal, and a one input for receiving a logical one signal, and means for selectively connecting the one input and the zero input to each switch output which is, in turn, connected to an input of an exclusive-OR gate.

Claim 10

The apparatus of claim 8 wherein the switches are programmable to selectively permit the connection of each of said switch inputs to each of said switch outputs.

Claim 11

The apparatus of claim 9, wherein each of the outputs of each of the switches can be programmed (a) to connect to a first signal input of the switch, (b) to connect to a second signal input of the switch, (c) to be set to a logical zero value, and (d) to be set to a logical one value.

Claim 12

The apparatus of claim 10, wherein each of said switches is adapted to be programmed by four bits.

Claim 13

A digital logic cell comprising: a. a set of exclusive-OR gates, each having at least two inputs and an output; b. a set of C-elements, each having at least two inputs and an output; c. a set of programmable switch assemblies having first, second, third and fourth signal leads, a logical one input lead for connection to a logical one source and a logical zero input lead for connection to a logical zero source; d. each of such switch assemblies comprising first and second single-pole, four-throw switches, (i) with regard to the first switch, the pole thereof being connected to the third signal lead of the switch assembly, a first throw being connected to the first signal lead, a second throw being connected to the second signal lead, a third throw being connected to the logical zero input lead and the fourth throw being connected to the logical one input lead, and (ii) with regard to the second switch, the pole thereof being connected to the fourth signal lead of the switch assembly, a first throw being connected to the first signal lead, a second throw being connected to the second signal lead, a third throw being connected to the logical zero input lead and the fourth throw being connected to the logical one input lead; e. the output of each exclusive-OR gate being connected to one of the first and second signal leads of first and second switch assemblies and each input of each exclusive-OR gate being connected to one of the third and fourth signal leads of each of two other switch assemblies; and f. the output of each C-element being connected to one of the first and second signal leads of third and fourth switch assemblies and each input of each C-element being connected to one of the third and fourth signal leads of each of two other switch assemblies.

Claim 14

A digital logic cell comprising: a. a set of exclusive-OR gates, each having at least two inputs and an output; b. a set of C-elements, each having at least two inputs and an output; c. a set of programmable switch assemblies having first, second, third and fourth signal leads, a logical one input lead for connection to a logical one source and a logical zero input lead for connection to a logical zero source; d. each of such switch assemblies comprising first and second single-pole, four-throw switches, (i) with regard to the first switch, the pole thereof being connected to the third signal lead of the switch assembly, a first throw being connected to the first signal lead, a second throw being connected to the second signal lead, a third throw being connected to the logical zero input lead and the fourth throw being connected to the logical one input lead, and (ii) with regard to the second switch, the pole thereof being connected to the fourth signal lead of the switch assembly, a first throw being connected to the first signal lead, a second throw being connected to the second signal lead, a third throw being connected to the logical zero input lead and the fourth throw being connected to the logical one input lead; e. the output of each exclusive-OR gate being connected to one of the first and second signal leads of first and second switch assemblies and each input of each exclusive-OR gate being connected to one of the third and fourth signal leads of each of two other switch assemblies; and f. the output of each C-element being connected to one of the first and second signal leads of third and fourth switch assemblies and each input of each C-element being connected to one of the third and fourth signal leads of each of two other switch assemblies.

Claim 15

A homogeneous array of digital logic cells, each cell comprising (a) a set of exclusive-OR elements, each having two inputs and an output; (b) a set of C-elements, each having two inputs and an output; and (c) a set of programmable switches selectively operable to operatively interconnect the exclusive-OR elements and C-elements within a cell and to operatively interconnect the elements on the boundaries of a cell with the elements of neighboring cells.

Claim 16

A homogeneous array of digital logic cells, each cell comprising (a) a set of exclusive-OR elements, each having two inputs and an output; (b) a set of C-elements, each having two inputs and an output; and (c) a set of programmable switches selectively operable to operatively interconnect the exclusive-OR elements and C-elements within a cell and to operatively interconnect the elements on the boundaries of a cell with the elements of neighboring cells.

Claim 17

The array of claim 13 wherein each switch comprises an assembly of first and second single-pole, four-throw (SP4T) switches, each such assembly having (i) first, second, third and fourth signal leads, (ii) a logical one input for connection to a logical one source and (iii) a logical zero input lead for connection to a logical zero source; the pole of the first switch being connected to provide the third signal lead of the switch assembly, a first throw of the first switch being connected to the first signal lead, a second throw thereof being connected to the second signal lead, a third throw thereof being connected to the logical zero input and the fourth throw thereof being connected to the logical one input; the pole of the second switch being connected to the fourth signal lead of the switch assembly, a first throw of the second switch being connected to the first signal lead, a second throw thereof being connected to the second signal lead, a third throw thereof being connected to the logical zero input and the fourth throw thereof being connected to the logical one input; the output of each exclusive-OR element being connected to one of the first and second signal leads of two such switch assemblies; each input of each exclusive-OR element being connected to one of the third and fourth signal leads of each of two other such switch assemblies; the output of each C-element being connected to one of the first and second signal leads of each of two switch assemblies; and each of the inputs of each C-element being connected to one of the third and fourth signal leads of each of two other switch assemblies.

Claim 18

The array of claim 14 formed of a two-dimensional matrix of cells.

Claim 19

The array of claim 14 formed of a three-dimensional matrix of cells.

Claim 20

A digital logic cell for use in implementing Petri Nets, comprising: a. a set of disjunctive means of a single type and a set of conjunctive means of a single type, each of the disjunctive and conjunctive means having at least two input leads and an output lead, (i) each disjunctive means having means for producing on its output lead a predetermined effect upon the arrival of a corresponding predetermined effects on one of its input leads, (ii) each conjunctive means having means for producing on its output lead a predetermined effect upon the arrival of corresponding predetermined effects on each of its input leads, such effects representing Petri Net tokens; and b. a set of programmable configuration switches for selectively, operatively interconnecting the disjunctive and conjunctive elements, each configuration switch having first and second inputs and at least one output.

Claim 21

A digital logic cell for use in implementing Petri Nets, comprising: a. a set of disjunctive means of a single type and a set of conjunctive means of a single type, each of the disjunctive and conjunctive means having at least two input leads and an output lead, (i) each disjunctive means having means for producing on its output lead a predetermined effect upon the arrival of a corresponding predetermined effects on one of its input leads, (ii) each conjunctive means having means for producing on its output lead a predetermined effect upon the arrival of corresponding predetermined effects on each of its input leads, such effects representing Petri Net tokens; and b. a set of programmable configuration switches for selectively, operatively interconnecting the disjunctive and conjunctive elements, each configuration switch having first and second inputs and at least one output.

Claim 22

The digital logic cell of claim 17 wherein the conjunctive elements and disjunctive elements are connectable by the configuration switches to form a Petri Net switch having first, second and third input leads and first and second output leads, and wherein an effect received at the third input lead causes an effect to be produced (a) on the first of such output leads if an effect is also received at the first of such input leads and (b) on the second of such output leads if an effect is also received at the second of such input leads, provided that no such input effect has previously caused an effect to be produced on one of such output leads.

Claim 23

An array of digital logic cells for use in implementing Petri Nets, comprising a plurality of cells each having (1) a set of disjunctive means of a single type, (2) a set of conjunctive means of a single type, and (3) a set of programmable configuration switches for selectively, operatively interconnecting disjunctive and conjunctive means; a. each of the disjunctive and conjunctive means having first and second input leads and an output lead; b. each disjunctive means having means for producing on its output lead a predetermined effect upon the arrival of a corresponding predetermined effect on one of its input leads; c. each conjunctive means having means for producing on its output lead a predetermined effect upon the arrival of corresponding predetermined effects on both of its input leads; d. such effects representing Petri Net tokens; e. each configuration switch having first and second input and at least one output; f. the conjunctive and disjunctive means of individual cells and groups of cells being connectable via programming of the configuration switches to implement Petri Nets which are safe and presistent, and in which each transition has no more than two shared input places and any transition with two shared input places has no other input places.

Claim 24

An array of digital logic cells for use in implementing Petri Nets, comprising a plurality of cells each having (1) a set of disjunctive means of a single type, (2) a set of conjunctive means of a single type, and (3) a set of programmable configuration switches for selectively, operatively interconnecting disjunctive and conjunctive means; a. each of the disjunctive and conjunctive means having first and second input leads and an output lead; b. each disjunctive means having means for producing on its output lead a predetermined effect upon the arrival of a corresponding predetermined effect on one of its input leads; c. each conjunctive means having means for producing on its output lead a predetermined effect upon the arrival of corresponding predetermined effects on both of its input leads; d. such effects representing Petri Net tokens; e. each configuration switch having first and second input and at least one output; f. the conjunctive and disjunctive means of individual cells and groups of cells being connectable via programming of the configuration switches to implement Petri Nets which are safe and presistent, and in which each transition has no more than two shared input places and any transition with two shared input places has no other input places.

Claim 25

An array of digital logic cells for use in implementing Petri Nets, comprising a plurality of cells each having (1) a set of disjunctive means of a single type, (2) a set of conjunctive means of a single type, and (3) a set of programmable configuration switches for selectively, operatively interconnecting disjunctive and conjunctive means; a. each of the disjunctive and conjunctive means having first and second input leads and an output lead; b. each disjunctive means having means for producing on its output lead a predetermined effect upon the arrival of a corresponding predetermined effect on one of its input leads; c. each conjunctive means having means for producing on its output lead a predetermined effect upon the arrival of corresponding predetermined effects on both of its input leads; d. such effects representing Petri Net tokens; e. each configuration switch having first and second inputs and at least one output; f. the conjunctive and disjunctive means of individual cells and groups of cells being connectable via programming of the configuration switches to form a Petri Net switch having first, second and third input leads and first and second output leads, and wherein an effect received at the third input lead causes an effect to be produced (a) on the first of such output leads if an effect if also received at the first of such input leads and (b) on the second of such output leads if an effect is also received at the second of such input leads, provided that no such input effect has previously caused an effect to be produced on one of such output leads.

Claim 26

An array of digital logic cells for use in implementing Petri Nets, comprising a plurality of cells each having (1) a set of disjunctive means of a single type, (2) a set of conjunctive means of a single type, and (3) a set of programmable configuration switches for selectively, operatively interconnecting disjunctive and conjunctive means; a. each of the disjunctive and conjunctive means having first and second input leads and an output lead; b. each disjunctive means having means for producing on its output lead a predetermined effect upon the arrival of a corresponding predetermined effect on one of its input leads; c. each conjunctive means having means for producing on its output lead a predetermined effect upon the arrival of corresponding predetermined effects on both of its input leads; d. such effects representing Petri Net tokens; e. each configuration switch having first and second inputs and at least one output; f. the conjunctive and disjunctive means of individual cells and groups of cells being connectable via programming of the configuration switches to form a Petri Net switch having first, second and third input leads and first and second output leads, and wherein an effect received at the third input lead causes an effect to be produced (a) on the first of such output leads if an effect if also received at the first of such input leads and (b) on the second of such output leads if an effect is also received at the second of such input leads, provided that no such input effect has previously caused an effect to be produced on one of such output leads.

Claim 27

A bipartite logic structure comprising a first set of nodes comprising conjunctive and disjunctive elements and a second set of nodes comprising means for selectively, operatively interconnecting the conjunctive and disjunctive elements; and wherein the first and second sets of nodes are disposed in a regular array structure such that the nodes of the first set and the nodes of the second set are disposed in an alternating relationship.

Claim 28

A bipartite logic structure comprising a first set of nodes comprising conjunctive and disjunctive elements and a second set of nodes comprising means for selectively, operatively interconnecting the conjunctive and disjunctive elements; and wherein the first and second sets of nodes are disposed in a regular array structure such that the nodes of the first set and the nodes of the second set are disposed in an alternating relationship.

Claim 29

The structure of claim 21 wherein the first and second sets of nodes are embodied in a semiconductor integrated circuit.