Rewritable programmable logic array

Claim 1

A rewritable programmable logic array (R-PLA), which loads a word pattern of bit personalities to generate specific logic function into memory cells from the word direction comprising: a SEARCH array (14) comprising bit lines (10), sense-drive word lines (15) having end terminals thereon and multi-emitter type bistable Current Mode Logic (CML) memory cells (11) at all intersections of said bit lines with said sense-drive word lines; a READ array (24) comprising word lines (20), sense-drive bit lines (25) having end terminals thereon and multi-emitter type bistable CML memory cells at all intersections of said word lines with said sense-drive word lines; a first two-channel selector (13) comprising first READ inputs (130) and first WRITE inputs (131) to which input signals are respectively supplied, the outputs of said first selector being connected to said bit lines of said SEARCH array; first sense-drive circuits (160) operable in a READ mode and a WRITE mode connected to said terminals of said sense-drive word lines of said SEARCH array, having first DRIVE inputs (161) and first WRITE pulse signal inputs (160) respectively receiving signals in said WRITE mode and having first READ outputs (12) for generating AND-function signals in response to said first READ inputs of said first selector in said READ mode; a second two-channel selector (23) comprising second READ inputs (230) and second WRITE inputs (231) to which input signals are respectively supplied, and second READ inputs of said second selector being connected to said first READ outputs of said first sense-drive circuits, the outputs of said second selector being connected to said word lines of said READ array; second sense-drive circuits (26) operable in a READ mode and a WRITE mode connected to said terminals of said sense-drive bit lines of said READ array, having second DRIVE inputs (261) and second WRITE pulse signal inputs (260) respectively receiving signals in said WRITE mode and having second READ outputs (22) for generating AND-function signals in response to said second READ inputs of said second selector in said READ mode; bit partitioning networks (3) having inputs (30) for receiving input variables and having outputs (130) connected to said first READ inputs of said first selector to deliver signals to said first selector; a WRITE address decoder (6) having inputs (60) for receiving WRITE address signals and outputs (61) connected, through means (8) for generating said first WRITE pulse signals, to said first WRITE pulse signal inputs of said first sense-drive circuit and also connected to said second WRITE inputs of said second selector, first READ/WRITE control circuits (5, 6, 7 and 8) including said means for generating said first WRITE pulse signals and connected to said first WRITE inputs to a selected control lines (SLI) of said first selector and to said first sense-drive circuits; and second READ/WRITE control circuits (5, 9) connected to said second selector and also to said second sense-drive circuits; whereby AND-functions are conducted by using one multi-emitter of a transistor in each said CML memory cell and an emitter of a reference transistor in each of said sense-drive circuits in the READ mode of said R-PLA.