US4084152A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Time shared programmable logic array
Assignee: International Business Machines Corp
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Filing: 1977-04-04
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Granted: 1978-04-11
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Expires: 1997-04-04
Abstract
Abstract This specification describes arrays for performing logic functions. In these arrays input variables are placed on a series of parallel input lines that intersect a number of parallel output lines in a grid of intersections. Field effect devices at these intersections have their gate terminals connected to one of the input lines and their source terminal connected to one of the output lines and through a load device to a source of potential. The drain terminals of these devices are either unconnected, connected directly to ground or connected to ground through one of two switching devices. The devices with unconnected drains are inoperative. The devices with their drains connected directly to ground are operative at all times. While the devices connected to ground through one of the switches are operative only when the switch is closed. The array can be time shared by two different logic functions by having one or the other of the switches off at any given time.
Inventors
- 👤 Gerald Bernard Long
- 👤 Ralph Charles Mitchell
- 👤 Shing Chou Pi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
218 words
In a logic performing arrangement including an array having a plurality of input lines intersected by a plurality of output lines with elements located in the form of a gated three terminal device at at least some of the intersections of the input and output lines with one of the terminals coupled to the input line and the other connected to the output line at that intersection so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines, the improvements comprising; a first group of said logic elements for performing a first logic function on input signals placed on the input lines of said array, a second logic group performing a second conflicting function on input signals placed on the input lines of the array, different switch means coupling each of said groups to source of excitation potential when the switch means is operative and uncoupling said group of devices from the source of excitation when the switch means is nonoperative so that logic performed in those two groups will depend on whether the said switch means is operative or nonoperative and, means for rendering said switch operative at different times whereby there is no conflict in the logic functions performed in the logic performing arrangement.
Claim 2
Dependent Claim
218 words
In a logic performing arrangement including an array having a plurality of input lines intersected by a plurality of output lines with elements located in the form of a gated three terminal device at at least some of the intersections of the input and output lines with one of the terminals coupled to the input line and the other connected to the output line at that intersection so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines, the improvements comprising; a first group of said logic elements for performing a first logic function on input signals placed on the input lines of said array, a second logic group performing a second conflicting function on input signals placed on the input lines of the array, different switch means coupling each of said groups to source of excitation potential when the switch means is operative and uncoupling said group of devices from the source of excitation when the switch means is nonoperative so that logic performed in those two groups will depend on whether the said switch means is operative or nonoperative and, means for rendering said switch operative at different times whereby there is no conflict in the logic functions performed in the logic performing arrangement.
Claim 3
Dependent Claim
32 words
The logic arrangement of claim 1 including a third group of said logic elements which are coupled to a source of excitation potential for operation with both the first and second groups.
Claim 4
Dependent Claim
24 words
The logic arrangement of claim 1 wherein said gated three terminal devices are field effect transistors each with a diode coupled to its source.
Claim 5
Dependent Claim
58 words
The logic arrangement of claim 3 wherein the gate of each said field effect transistor is connected to an input line of the array, the source and drains of said field effect transistor are connected in series with said source of excitation potential, the diode coupled to the field effect transistor, and one of the different switch means.
Claim 6
Dependent Claim
30 words
The logic arrangement of claim 1 wherein said gated three-terminal devices are MNOS devices to prevent conduction during the time the devices are decoupled from the source of excitation potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-10 | 1981-10-10 | 1982-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-10 | 1985-10-10 | 1986-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-10 | 1989-10-10 | 1990-04-11 | $7700.00 | Window Closed / Lapsed |