US4233667A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Demand powered programmable logic array
Assignee: International Business Machines Corp
•
Filing: 1978-10-23
•
Granted: 1980-11-11
•
Expires: 1998-10-23
Abstract
Abstract This specification describes a programmable logic array (PLA) for performing logic functions on binary variables in a plurality of sequentially functioning arrays in which at least one of the arrays is conditionally powered when and only when the binary variables are supplied to the PLA in a logically useful combination.
Inventors
- 👤 William T. Devine
- 👤 William Gianopulos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:20
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
122 words
In a programmable logic array of the type which operates on binary data variables in an AND matrix of logic performing elements to generate product terms and supplies them to an OR matrix of logic performing elements which in turn feeds sums of these product terms into a storage means to provide those output signals in various combinations as inputs to the AND array, the improvement comprising: logic means including at least logic performing elements in the AND matrix to generate a control signal from said binary data variables and powering means responsive to said control signal to conditionally power at least a portion of one of the logic performing parts of the programmable logic array in response to said control signal.
Claim 2
Dependent Claim
122 words
In a programmable logic array of the type which operates on binary data variables in an AND matrix of logic performing elements to generate product terms and supplies them to an OR matrix of logic performing elements which in turn feeds sums of these product terms into a storage means to provide those output signals in various combinations as inputs to the AND array, the improvement comprising: logic means including at least logic performing elements in the AND matrix to generate a control signal from said binary data variables and powering means responsive to said control signal to conditionally power at least a portion of one of the logic performing parts of the programmable logic array in response to said control signal.
Claim 3
Dependent Claim
21 words
The programmable logic array of claim 1 wherein said at least one of the logic performing parts is the OR matrix.
Claim 4
Dependent Claim
21 words
The programmable logic array of claims 1 or 2 wherein said logic means includes logic performing elements in the OR matrix.
Claim 5
Dependent Claim
21 words
The programmable logic array of claims 1, or 2 wherein said powering means includes logic performing elements in the OR matrix.
Claim 6
Dependent Claim
20 words
The programmable logic array of claims 1 or 2 wherein said storage means is conditionally powered by said powering means.
Claim 7
Dependent Claim
102 words
In a programmable logic array for generating logic functions from binary data variables of the type which includes an AND matrix generating inputs to an OR matrix which in turn feeds its output signals into a storage means that provides output signals which can be used in various combinations as inputs to the AND matrix, the method of conditionally powering at least a portion of one of the logic performing matrices or storage means as a function of said binary data variables when and only when said binary data variables are supplied to the programmable logic array in a logically useful combination.
Claim 8
Dependent Claim
102 words
In a programmable logic array for generating logic functions from binary data variables of the type which includes an AND matrix generating inputs to an OR matrix which in turn feeds its output signals into a storage means that provides output signals which can be used in various combinations as inputs to the AND matrix, the method of conditionally powering at least a portion of one of the logic performing matrices or storage means as a function of said binary data variables when and only when said binary data variables are supplied to the programmable logic array in a logically useful combination.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-11 | 1984-05-12 | 1984-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-11 | 1988-05-12 | 1988-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-11 | 1992-05-12 | 1992-11-11 | $7700.00 | Window Closed / Lapsed |