Storage logic array having two conductor data column

Claim 2

An integrated circuit storage logic array comprising: at least one data column having first and second data column conductors; a plurality of rows disposed substantially orthogonal to said column, each row comprising a row conductor; clock means for generating a plurality of phase-displaced clock signals; a storage cell operatively associated with said data column, said storage cell having a memory element, output means responsive to said clock means for transferring data from said memory element to said first and second data column conductors, and input means coupled for transferring data from said first and second data column conductors to said memory element; and a plurality of functionally distinct logic cells connected between selected column and row conductors and adapted to be actuated by said clock means to manipulate data among said selected column and row conductors.

Claim 3

The storage logic array of claim 1 further comprising at least one OR column having an OR column conductor.

Claim 4

The storage logic array of claim 2 wherein said memory element is a flip-flop.

Claim 5

The storage logic array of claim 3 further comprising means for precharging said column and row conductors to a predetermined level in response to a first of said clock signals.

Claim 6

The storage logic array of claim 4 wherein said flip-flop includes a pair of complementary input/output ports, one of said ports being coupled to said first data column conductor and the other of said ports being couupled to the second data column conductor.

Claim 7

The storage logic array of claim 5 wherein said output means is coupled to said clock means and data from respective input/output ports of said flip-flop is switched by said output means to said first and second data column conductors in response to a second of said clock signals.

Claim 8

The storage logic array of claim 6 wherein said clock means generates six phase-displaced clock signals.

Claim 9

The storage logic array of claim 7 wherein at least one of said logic cells is connected to cause a row conductor to assume a binary state determined by the binary state of a data column conductor in response to the third of said clock signals.

Claim 10

The storage logic array of claim 7 wherein at least one of said logic cells is connected to cause said OR column conductor to assume a binary state determined by the binary state of a row conductor in response to the fourth of said clock signals.

Claim 11

The storage logic array of claim 7 including means for precharging said data column conductors a second time to a predetermined level in response to the fourth of said clock signals.

Claim 12

The storage logic array of claim 9 including means for precharging said data column conductors a second time to a predetermined level in response to the fourth of said clock signals.

Claim 13

The storage logic array of claim 7 or 10 wherein at least one of said logic cells is connected to cause a row conductor to assume a binary state determined by the binary state of said OR column conductor in response to the fifth of said clock signals.

Claim 14

The storage logic array of claim 7 or 10 wherein at least one of said logic cells is connected to cause a data column conductor to assume a binary state determined by the binary state of a row conductor in response to the sixth of said clock signals.

Claim 15

The storage logic array of claim 13 wherein said input means is coupled to said clock means and data from said first and second data column conductors is switched to corresponding input/output ports of said flip-flop by said input means in response to the sixth of said clock signals.

Claim 16

The storage logic array of claim 8 wherein said logic cell comprises a plurality of transistors adapted to transfer to said row conductor the same binary state that is on said data column conductor.

Claim 17

The storage logic array of claim 8 wherein said logic cell comprises a plurality of transistors adapted to transfer to said row conductor the opposite binary state of that which is on said data column conductor.

Claim 18

The storage logic array of claim 12 wherein said logic cell comprises a plurality of transistors adapted to transfer to said row conductor the same binary state that is on said OR column conductor.

Claim 19

The storage logic array of claim 12 wherein said logic cell comprises a plurality of transistors adapted to transfer to said row conductor the opposite binary state of that which is on said OR column conductor.

Claim 20

The storage logic array of claim 9 wherein said logic cell comprises a plurality of transistors adapted to transfer to said OR column conductor the same binary state that is on said row conductor.

Claim 21

The storage logic array of claim 9 wherein said logic cell comprises a plurality of transistors adapted to transfer to said OR column conductor the opposite binary state of that which is on said row conductor.

Claim 22

The storage logic array of claim 13 wherein said logic cell comprises a plurality of transistors adapted to transfer to said data column conductor the same binary state that is on said row conductor.

Claim 23

The storage logic array of claim 13 wherein said logic cell comprises a plurality of transistors adapted to transfer to said data column conductor the opposite binary state of that which is on said row conductor.

Claim 24

An integrated circuit storage logic array comprising: at least one data column having first and second data column conductors; at least one OR column having an OR column conductor; a plurality of rows disposed substantially orthogonal to said columns, each row comprising a row conductor; a storage cell operatively associated with said data column and having a memory element with a pair of complementary input/output ports, each of said ports being coupled to a respective one of said data column conductors; clock means for generating six phase-displaced clock signals; means for precharging said column and row conductors to a predetermined level in response to the first of said clock signals; output means associated with said input/output ports for switching data from said ports to respective data column conductors in response to the second of said clock signals; a first logic cell connected to cause a row conductor to assume a binary state determined by the binary state of a data column conductor in response to the third of said clock signals; a second logic cell connected to cause an OR column conductor to assume a binary state determined by the binary state of a row conductor in response to the fourth of said clock signals; a third logic cell connected to cause a row conductor to assume a binary state determined by the binary state of an OR column conductor in response to the fifth of said clock signals; and a fourth logic cell connected to cause one of said data column conductors to assume a binary state determined by the binary state of a row conductor in response to the sixth of said clock signals.

Claim 25

An integrated circuit storage logic array comprising: at least one data column having first and second data column conductors; at least one OR column having an OR column conductor; a plurality of rows disposed substantially orthogonal to said columns, each row comprising a row conductor; a storage cell operatively associated with said data column and having a memory element with a pair of complementary input/output ports, each of said ports being coupled to a respective one of said data column conductors; clock means for generating six phase-displaced clock signals; means for precharging said column and row conductors to a predetermined level in response to the first of said clock signals; output means associated with said input/output ports for switching data from said ports to respective data column conductors in response to the second of said clock signals; a first logic cell connected to cause a row conductor to assume a binary state determined by the binary state of a data column conductor in response to the third of said clock signals; a second logic cell connected to cause an OR column conductor to assume a binary state determined by the binary state of a row conductor in response to the fourth of said clock signals; a third logic cell connected to cause a row conductor to assume a binary state determined by the binary state of an OR column conductor in response to the fifth of said clock signals; and a fourth logic cell connected to cause one of said data column conductors to assume a binary state determined by the binary state of a row conductor in response to the sixth of said clock signals.

Claim 26

The storage logic array of claim 23 further comprising input means associated with said input/output ports for switching data from said first and second data column conductors to corresponding ports in response to the sixth of said clock signals.

Claim 27

The storage logic array of claim 23 or 24 including means for precharging said data column conductors a second time to a predetermined level in response to the fourth of said clock signals.

Claim 28

An integrated circuit storage logic array comprising: at least one data column having first and second data column conductors; a plurality of rows disposed substantially orthognal to said column, each row comprising a row conductor; clock means for generating four phase-displaced clock periods; a storage cell operatively associated with said data column, said storage cell having a flip-flop memory element, output means responsive to said clock means for transferring data from said memory element to said first and second data column conductors, and input means coupled for transferring data from said first and second data column conductors to said memory element; a plurality of logic cells connected between selected column and row conductors; and at least one OR column having an OR column conductor.

Claim 29

An integrated circuit storage logic array comprising: at least one data column having first and second data column conductors; a plurality of rows disposed substantially orthognal to said column, each row comprising a row conductor; clock means for generating four phase-displaced clock periods; a storage cell operatively associated with said data column, said storage cell having a flip-flop memory element, output means responsive to said clock means for transferring data from said memory element to said first and second data column conductors, and input means coupled for transferring data from said first and second data column conductors to said memory element; a plurality of logic cells connected between selected column and row conductors; and at least one OR column having an OR column conductor.

Claim 30

The storage logic array of claim 26 further comprising means for precharging said data column conductors to a predetermined level during the first of said clock periods and wherein at least one of said logic cells is connected to cause an OR column conductor to assume a binary state determined by the binary state of a row conductor during said first clock period.

Claim 31

The storage logic array of claim 27 further comprising means for generating an additional clock period which begins when the first clock period begins and ends when the second clock period begins.

Claim 32

The storage logic array of claim 28 wherein another of said logic cells is connected to cause a row conductor to assume a binary state determined by the binary state of an OR column conductor after said first clock period and during said additional clock period.

Claim 33

The storage logic array of claim 29 wherein another of said logic cells is connected to cause a particular one of said data column conductors to assume a binary state determined by the binary state of a row conductor during the second of said clock periods.

Claim 34

The storage logic array of claim 30 wherein said input means of said storage cell changes the state of said flip-flop in response to a predetermined binary state being assumed by said particular data column conductor.

Claim 35

The storage logic array of claim 31 further comprising means for precharging said row conductors to a predetermined level during the third of said clock periods and wherein said output means of said storage cell switches data from said flip-flop to said data column conductors during said third clock period.

Claim 36

The storage logic array of claim 32 wherein another of said logic cells is connected to cause a row conductor to assume a binary state determined by the binary state of a data column conductor during the fourth of said clock periods.

Claim 37

The storage logic array of claim 33 further comprising means for precharging said OR column conductor to a predetermined level during said fourth clock period.

Claim 38

The storage logic array of claim 26 or 34 wherein said logic cells each comprise a plurality of transistors.

Claim 39

The storage logic array of claim 26 wherein said OR column further comprises an inverted OR column conductor.

Claim 40

The storage logic array of claim 36 wherein one of said logic cells is connected to invert data from a row conductor and transfer the inverted data to an OR column conductor.

Claim 41

The storage logic array of claim 36 further comprising means for precharging said data column conductors to a predetermined level during the first of said clock periods and wherein one of said logic cells is connected to cause a row conductor to assume a binary state determined by the binary state of an OR column conductor during said first clock period.

Claim 42

The storage logic array of claim 38 wherein another of said logic cells is connected to cause a particular one of said data column conductors to assume a binary state determined by the binary state of a row conductor during the second of said clock periods.

Claim 43

The storage logic array of claim 39 wherein said input means of said storage cell changes the state of said flip-flop in response to a predetermined binary state being assumed by said particular data column conductor.

Claim 44

The storage logic array of claim 40 further comprising means for precharging said row conductors to a predetermined level during the third of said clock periods and wherein said output means of said storage cell switches data from said flip-flop to said data column conductors during said third clock period.

Claim 45

The storage logic array of claim 41 wherein another of said logic cells is connected to cause a row conductor to assume a binary state determined by the binary state of a data column conductor during the fourth of said clock periods.

Claim 46

The storage logic array of claim 36 or 42 wherein said OR column conductor and inverted OR column conductor each has a static pull-up transistor coupled thereto.

Claim 47

The storage logic array of claim 42 wherein said logic cells each comprise a plurality of transistors.