High speed sense amplifier for MOS random access memory

Claim 2

In a memory system of the type having an array of rows and columns of memory cells and a sense amplifier positioned at the center of each column line, the sense amplifier comprising a pair of cross coupled driver transistors and a load transistor for each driver transistor, a supply voltage of a given value for the memory system, each of said transistors having a source-to-drain path and a gate, the improvement comprising a pair of switching devices each connected to discharge the gate of one of the load transistors, each of the switching devices having a source-to-drain path and a gate and a selected voltage applied to their gates which is less than said supply voltage, coupling means for applying a voltage to the gates of the load transistors sufficient to turn on the load transistors at a selected time, and means for precharging the column lines prior to said selected time.

Claim 3

Apparatus according to claim 1 wherein the sense amplifiers include means for connecting the sources of the driver transistors to reference potential, and such means are sequentially actuated during a period in an operating cycle beginning prior to said selected time and ending after said selected time.

Claim 4

Apparatus according to claim 2 wherein said means includes a pair of MOS transistors which are selectively actuated at differing times.

Claim 5

Apparatus according to claim 3 wherein the per bit ratio of width to length of the channel of one of the pair of MOS transistors is very small compared to that of the channels of the driver transistors.

Claim 6

Apparatus according to claim 4 wherein said one of the pair of MOS transistors is turned on during a given time prior to said selected time during an operating cycle.

Claim 7

Apparatus according to claim 5 wherein the coupling means comprises gated capacitors having one side connected to a clock source exhibiting a change in voltage level at said selected time during each operating cycle.

Claim 8

In a sense amplifier for a semiconductor memory of the type having a pair of cross-coupled driver transistors and a pair of load transistors connecting the driver transistors to a supply voltage, each of the driver and load transistors having a source, drain and a gate, each driver transistor having its drain connected to one of a pair of opposing digit lines which have a plurality of memory cells connected thereto, two separate control transistors each having a source-to-drain path connecting the sources of the driver transistors to a reference potential, each of the control transistors having a gate, means for supplying control voltages to the gates of the control transistors for actuating one of the control transistors at a first time in an operating cycle and activating the other of the control transistors at a selected time later than the first time in each operating cycle, the improvement comprising means for connecting the gates of the load transistors to the digit lines whereby the load transistor for the digit line which goes to logic zero is rendered non-conductive at said second time.

Claim 9

In a sense amplifier for a semiconductor memory of the type having a pair of cross-coupled driver transistors and a pair of load transistors connecting the driver transistors to a supply voltage, each of the driver and load transistors having a source, drain and a gate, each driver transistor having its drain connected to one of a pair of opposing digit lines which have a plurality of memory cells connected thereto, two separate control transistors each having a source-to-drain path connecting the sources of the driver transistors to a reference potential, each of the control transistors having a gate, means for supplying control voltages to the gates of the control transistors for actuating one of the control transistors at a first time in an operating cycle and activating the other of the control transistors at a selected time later than the first time in each operating cycle, the improvement comprising means for connecting the gates of the load transistors to the digit lines whereby the load transistor for the digit line which goes to logic zero is rendered non-conductive at said second time.

Claim 10

A sense amplifier according to claim 7 wherein said one of the control transistors conducts much less current than the other of the control transistors.

Claim 11

A sense amplifier according to claim 8 wherein the means for connecting the gates of the load transistor to the digit lines comprises a pair of MOS transistors, each of the MOS transistors having a gate, and means connecting a bias voltage less than said supply voltage to the gates of the MOS transistors.

Claim 12

A sense amplifier according to claim 9 wherein a capacitor means separately couples a clock source to said gates of the load transistors, the clock source producing a voltage no later than said second time in each operating cycle.

Claim 13

A sense amplifier according to claim 10 wherein means are provided for precharging the digit lines to a voltage level near the supply voltage, at a time prior to said first time in such operating cycle.