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US4031522A Expired / Lapsed US ⏱️ 0.0 years remaining

Ultra high sensitivity sense amplifier for memories employing single transistor cells

Assignee: Samsung Electronics Co Ltd
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Filing: 1975-07-10
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Granted: 1977-06-21
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Expires: 1995-07-10
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Abstract

Abstract This disclosure relates to a high impedance regenerative differential sense amplifier for use with an integrated circuit memory array of single transistor cells. Each of the sense amplifiers is formed of a cross coupled latch connected to the respective columns by source followers and leads from the latch drive write back gates coupled to the respective columns so as to restore a "zero" level of a cell and also leave a precharged "one" level with the cell by charging the appropriate column. The respective columns are initially precharged and balanced and then driven by negative going signals.

Inventors

  • 👤 John Anthony Reed
  • 👤 Joel Allen Karp

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 12:32
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; H03K3/356086; H03K3/356095

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 116 words
A differential sense amplifier and restore circuitry comprising: a pair of sense conductors; a pair of transistors cross-coupled to form a latch to sense a difference in voltage potential between said sense conductors, said latch having a pair of output leads and a pair of input leads; a pair of source followers, each coupled between one of said sense conductors and one of said input leads to receive an input signal from one or the other of said sense conductors; and a pair of write-back transistors, each coupled between one of said output leads and one of said sense conductors to supply a restore signal to the sense conductor from which an input signal was received.
Claim 2
Dependent Claim 116 words
A differential sense amplifier and restore circuitry comprising: a pair of sense conductors; a pair of transistors cross-coupled to form a latch to sense a difference in voltage potential between said sense conductors, said latch having a pair of output leads and a pair of input leads; a pair of source followers, each coupled between one of said sense conductors and one of said input leads to receive an input signal from one or the other of said sense conductors; and a pair of write-back transistors, each coupled between one of said output leads and one of said sense conductors to supply a restore signal to the sense conductor from which an input signal was received.
Claim 3
Dependent Claim 20 words
A differential sense amplifier and restore circuitry according to claim 1 wherein: said pair of transistors are field effect transistors.
Claim 4
Dependent Claim 19 words
A differential sense amplifier and restore circuitry according to claim 1 wherein: said source followers are field effect transistors.
Claim 5
Dependent Claim 19 words
A differential sense amplifier and restore circuitry according to claim 1 wherein: said write-back transistors are field effect transistors.
Claim 6
Dependent Claim 27 words
A differential sense amplifier and restore circuitry according to claim 2 including: a reset field effect transistor coupled to said pair of transistors to reset said latch.
Claim 7
Dependent Claim 32 words
A differential sense amplifier and restore circuitry according to claim 5 including: a clock source field effect transistor coupled to said pair of transistors to supply a negative going clock signal thereto.
Claim 8
Dependent Claim 104 words
A differential sense amplifier and restore circuitry comprising: a single MOS integrated circuit chip, said chip including: a pair of sense conductors; a pair of transistors cross-coupled to form a latch to sense a difference in voltage potential between said sense conductors, said latch having a pair of output leads and a pair of input leads; a pair of source followers, each coupled between one of said sense conductors and one of said input leads; and a pair of write-back transistors, each coupled between one of said output leads and one of said sense conductors to discharge that sense conductor having a lower potential.
Claim 9
Dependent Claim 104 words
A differential sense amplifier and restore circuitry comprising: a single MOS integrated circuit chip, said chip including: a pair of sense conductors; a pair of transistors cross-coupled to form a latch to sense a difference in voltage potential between said sense conductors, said latch having a pair of output leads and a pair of input leads; a pair of source followers, each coupled between one of said sense conductors and one of said input leads; and a pair of write-back transistors, each coupled between one of said output leads and one of said sense conductors to discharge that sense conductor having a lower potential.
Claim 10
Dependent Claim 20 words
A differential sense amplifier and restore circuitry according to claim 7 wherein: said pair of transistors are field effect transistors.
Claim 11
Dependent Claim 27 words
A differential sense amplifier and restore circuitry according to claim 8 including: a reset field effect transistor coupled to said pair of transistors to reset said latch.
Claim 12
Dependent Claim 32 words
A differential sense amplifier and restore circuitry according to claim 9 including: a clock source field effect transistor coupled to said pair of transistors to supply a negative going clock signal thereto.

References Cited (Backward Citations)

US3806898A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-06-20 1980-12-20 1981-06-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-06-20 1984-12-20 1985-06-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-06-20 1988-12-20 1989-06-21 $7700.00 Window Closed / Lapsed

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