OR Product term function in the search array of a PLA

Claim 2

In a programmed logic array including a search array and an OR array, with the search array including a plurality of FET array devices arranged into rows and columns with the gates thereof in each row selectively connected to a respective row input signal line and with the source/drain paths thereof in each column connected to a respective product term output line, and with the OR array including a plurality of FET array devices arranged into rows and columns, with the gates thereof in each column selectively connected to a respective one of said product term output lines and with a first source/drain path terminal thereof in each row connected to a first polarity reference potential and a second source/drain path terminal thereof in each row connected to a second polarity reference potential and also connected to an output node, the improvement comprising: a first one of said columns in said search array having the source/drain path of said FET array devices therein connected between a reference potential of said first polarity and a respective one of said product term lines which is precharged to said second polarity, for performing first-type logical functions; a second one of said columns in said search array having the source/drain path of said FET array devices therein connected between a reference potential of said second polarity and a respective one of said product term lines which is precharged to said first polarity, for performing second-type logical functions.

Claim 3

In a programmed logic array including a search array and an OR array, with the search array including a plurality of FET array devices arranged into rows and columns, with the gates thereof in each row selectively connected to a respective row input signal line for providing input logical signals during a second period following a first precharged period and with the source/drain paths thereof in each column connected to a respective product term output line, and with the OR array including a plurality of FET array devices arranged into rows and columns, with the gates thereof in each column selectively connected to a respective one of said product term output lines and with the source thereof in each row connected to a first polarity reference potential and drain thereof in each row connected to a second polarity reference potential and also connected through a signal inverter to an output node, the improvement comprising: a first one of said columns in said search array having the source/drain path of said FET array devices therein connected between a reference potential of said first polarity and a respective one of said product term lines which is precharged to said second polarity during said first period, for performing negative logical functions during said second period; a second one of said columns in said search array having the source/drain path of said FET array devices therein connected between a reference potential of said second polarity and a respective one of said product term lines which is precharged to said first polarity during said first period, for performing positive logical functions during said second period.

Claim 4

In a programmed logic array including a search array and an OR array, with the search array including a plurality of FET array devices arranged into rows and columns, with the gates thereof in each row selectively connected to a respective row input signal line for providing input logical signals during a second period following a first precharged period and with the source/drain paths thereof in each column connected to a respective product term output line, and with the OR array including a plurality of FET array devices arranged into rows and columns, with the gates thereof in each column selectively connected to a respective one of said product term output lines and with the source thereof in each row connected to a first polarity reference potential and drain thereof in each row connected to a second polarity reference potential and also connected through a signal inverter to an output node, the improvement comprising: a first one of said columns in said search array having the source/drain path of said FET array devices therein connected between a reference potential of said first polarity and a respective one of said product term lines which is precharged to said second polarity during said first period, for performing negative logical functions during said second period; a second one of said columns in said search array having the source/drain path of said FET array devices therein connected between a reference potential of said second polarity and a respective one of said product term lines which is precharged to said first polarity during said first period, for performing positive logical functions during said second period.

Claim 5

In a programmed logic array including a search array having signal output lines connected to the inputs of an OR array, with the search array including a plurality of FET array devices arranged into rows and columns, with the gates of FET array devices in each row selectively connected to a respective row input signal line, the improvement comprising: a first one of said columns in said search array having the source/drain path of said FET array devices therein connected between a first polarity precharged one of said signal output lines and a second polarity reference voltage, for providing an AND logical function; a second one of said columns in said search array having the source/drain path of said FET array devices therein connected between a second one of said signal output lines precharged to said second polarity and a reference voltage of said first polarity, for providing an OR logical function.

Claim 6

In a programmed logic array including a search array having signal output lines connected to the inputs of an OR array, with the search array including a plurality of FET array devices arranged into rows and columns, with the gates of FET array devices in each row selectively connected to a respective row input signal line, the improvement comprising: a first one of said columns in said search array having the source/drain path of said FET array devices therein connected between a first polarity precharged one of said signal output lines and a second polarity reference voltage, for providing an AND logical function; a second one of said columns in said search array having the source/drain path of said FET array devices therein connected between a second one of said signal output lines precharged to said second polarity and a reference voltage of said first polarity, for providing an OR logical function.

Claim 7

In a programmed logic array of the type which operates on binary variables in an AND array matrix of logic performing elements to generate product terms, said array elements including a first plurality of FET devices having their drains connected in common with a first product term output line and a first precharge switching device to a relatively high potential and their sources connected in common to a relatively low potential, the improvement for selectively providing an OR term in said AND array, comprising: a second plurality of FET devices in said AND array having their sources connected in common to said relatively high potential and their drains connected in common with a second product term output line and a second precharge switching device to said low potential; whereby OR terms are provided in said AND array.

Claim 8

In a programmed logic array of the type which operates on binary variables in an AND array matrix of logic performing elements to generate product terms, said array elements including a first plurality of FET devices having their drains connected in common with a first product term output line and a first precharge switching device to a relatively high potential and their sources connected in common to a relatively low potential, the improvement for selectively providing an OR term in said AND array, comprising: a second plurality of FET devices in said AND array having their sources connected in common to said relatively high potential and their drains connected in common with a second product term output line and a second precharge switching device to said low potential; whereby OR terms are provided in said AND array.