US4371963A — Method and apparatus for detecting and correcting…

Claim 1

Independent Claim 203 words

An error detection and correction system comprising: means for storing data including a first section, said data being stored in said first section in rows and columns, with a predetermined number of said rows of data forming a block in said first section; first means for generating and storing first check bits for said rows of data; and error correcting means, including: second means for generating check bits for said columns of data so as to produce a check word for each said block; a second section for storing said check words; and processor means operatively coupling said first and second means with said first and second sections; said processor means including: means for detecting an error in one of said rows as indicated by the associated said first check bit with the row containing an error being referred to as an error row; third means for generating a new check word for all said rows of data except said error row in the associated said block when an error row is found by said detecting means; and means for Exclusive ORing said new check word with the said check word for said block to thereby obtain corrected data for said error row.

Claim 2

Dependent Claim 203 words

An error detection and correction system comprising: means for storing data including a first section, said data being stored in said first section in rows and columns, with a predetermined number of said rows of data forming a block in said first section; first means for generating and storing first check bits for said rows of data; and error correcting means, including: second means for generating check bits for said columns of data so as to produce a check word for each said block; a second section for storing said check words; and processor means operatively coupling said first and second means with said first and second sections; said processor means including: means for detecting an error in one of said rows as indicated by the associated said first check bit with the row containing an error being referred to as an error row; third means for generating a new check word for all said rows of data except said error row in the associated said block when an error row is found by said detecting means; and means for Exclusive ORing said new check word with the said check word for said block to thereby obtain corrected data for said error row.

Claim 3

Dependent Claim 121 words

The error detection and correction system as claimed in claim 1 in which said processor means further comprises: a first plurality of Exclusive OR gates to Exclusive OR a new row of data (which is to be written into a selected said row in a selected said block) with the row of data which is to be replaced by said new row of data to thereby produce an intermediate check word for said selected block; a second plurality of Exclusive OR gates to Exclusive OR said intermediate check word with said check word associated with said selected block to produce a revised said check word; and means for writing said revised check word in said second section for said selected block.

Claim 4

Dependent Claim 53 words

The error detection and correction system as claimed in claim 2 in which said processor means further comprises: a register for storing said row of data which is to be replaced by said new row of data to enable the Exclusive ORing at said first plurality of Exclusive OR gates to be effected.

Claim 5

Dependent Claim 72 words

The error detection and correction system as claimed in claim 3 in which said writing means includes a multiplexer having first and second states to enable said revised check word from second plurality of Exclusive OR gates to be written in said second section when said multiplexer is in said first state, and to enable said processor means to write into said second section when said multiplexer is in said second state.

Claim 6

Independent Claim 210 words

A method of detecting and correcting errors in a memory, comprising the steps: (a) dividing said memory into a predetermined number of blocks, with data being stored in rows and columns in each said block; (b) calculating a first check bit for each said row of data; (c) calculating a second check bit for each of said columns of data in a said block to form a check word for each said block; (d) using said first check to detect an error in one of said rows of data within a said block; and (e) using the associated said said check word for the associated said block containing said error to correct any errors which exist in said row of data containing said error; said step (e) comprising the steps: (e-1) generating a new check word for all said rows of data except said row of data containing said error (hereinafter called error row) in the associated said block in which said error row is located by Exclusive ORing all said rows of data except said error row, and (e-2) Exclusive ORing said new check word with the associated said check word for said block containing said error row to thereby obtain corrected data for the entire said error row.

Claim 7

Independent Claim 210 words

A method of detecting and correcting errors in a memory, comprising the steps: (a) dividing said memory into a predetermined number of blocks, with data being stored in rows and columns in each said block; (b) calculating a first check bit for each said row of data; (c) calculating a second check bit for each of said columns of data in a said block to form a check word for each said block; (d) using said first check to detect an error in one of said rows of data within a said block; and (e) using the associated said said check word for the associated said block containing said error to correct any errors which exist in said row of data containing said error; said step (e) comprising the steps: (e-1) generating a new check word for all said rows of data except said row of data containing said error (hereinafter called error row) in the associated said block in which said error row is located by Exclusive ORing all said rows of data except said error row, and (e-2) Exclusive ORing said new check word with the associated said check word for said block containing said error row to thereby obtain corrected data for the entire said error row.

Claim 8

Dependent Claim 107 words

The method as claimed in claim 5 in which said step (c) comprises, during a writing operation in which a revised row of data is to be written into memory, the steps: (c-1) Exclusive ORing said revised row of data with said row of data in memory which is to be changed to produce an intermediate check word for the associated said block containing said row of data which is to be changed; (c-2) Exclusive ORing said intermediate check word with said check word for the associated said block containing said row of data in memory which is to be changed to produce a revised check word.

Claim 9

Dependent Claim 38 words

The method as claimed in claim 6 in which said step (c-1) is effected by a first plurality of Exclusive OR gates and in which said step (c-2) is effected by a second plurality of Exclusive OR gates.

Claim 10

Dependent Claim 43 words

The method as claimed in claim 6 in which said step (c) further comprises the step: (c-3) writing said revised row of data into its associated said block in memory and substantially simultaneously writing said revised check word into an associated memory section.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1986-01-31	1986-08-02	1987-02-01	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1990-01-31	1990-08-02	1991-02-01	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1994-01-31	1994-08-02	1995-02-01	$7700.00	Window Closed / Lapsed

Method and apparatus for detecting and correcting errors in a memory

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