Patent US2333712A successfully refreshed from Google Patents.
US4486705A
Expired / Lapsed
US
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Method of testing networks on a wafer having grounding points on its periphery
Assignee: Unisys Corp
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Filing: 1983-12-02
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Granted: 1984-12-04
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Expires: 2003-12-02
Abstract
Abstract Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1, is a network 11'0 interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12' exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.
Inventors
- 👤 Herbert Stopper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:24
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; H10P74/232; G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; H10P74/27; H10P74/273; H05; H05K; H05K1/00; H05K1/02; H05K1/0286
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
227 words
A method of testing a wafer having a plurality of networks formed thereon for interconnecting a plurality of integrated circuit chips, each said network including at least one power supply lead and power pad for supplying power to said integrated circuit chips, a plurality of logic lines and pad lines, each of said pad lines being connected to a logic input or output point as a node of one of said chips and having a single coupling to one of said logic lines and a position on said wafer, the intercoupling of said logic lines defining the intercoupling connection of the chips of each said network, each network further including at least one test lead from a terminal of the network to a grounding point on the periphery of said wafer, the method comprising: connecting ground to at least one of said test leads at said grounding point; connecting a probe to a logic input or output point in said network which is connected to said test lead if the network is properly connected; and passing a current through said network from said logic input or output point to said ground and measuring the electrical resistance through the line during testing to determine whether the measured resistance falls within expected normal inherent resistance of the measured line or is above or below the expected normal inherent resistance.
Claim 2
Independent Claim
227 words
A method of testing a wafer having a plurality of networks formed thereon for interconnecting a plurality of integrated circuit chips, each said network including at least one power supply lead and power pad for supplying power to said integrated circuit chips, a plurality of logic lines and pad lines, each of said pad lines being connected to a logic input or output point as a node of one of said chips and having a single coupling to one of said logic lines and a position on said wafer, the intercoupling of said logic lines defining the intercoupling connection of the chips of each said network, each network further including at least one test lead from a terminal of the network to a grounding point on the periphery of said wafer, the method comprising: connecting ground to at least one of said test leads at said grounding point; connecting a probe to a logic input or output point in said network which is connected to said test lead if the network is properly connected; and passing a current through said network from said logic input or output point to said ground and measuring the electrical resistance through the line during testing to determine whether the measured resistance falls within expected normal inherent resistance of the measured line or is above or below the expected normal inherent resistance.
Claim 3
Dependent Claim
88 words
A method of testing a wafer network according to claim 1 wherein: a circumferentially disposed grounding ring is placed in contact with said grounding points and said grounding ring is connected to ground, and wherein, each of said nodes is contacted with a probe of a resistance measurement device in succession and the resistance of the network line is measured during testing to determine whether the measured resistance falls within expected normal inherent resistance of the measured line or is above or below the expected normal inherent resistance.
Claim 4
Dependent Claim
94 words
A method according to claim 2 wherein said wafer has each network defined programmatically and wherein the resistance testing determines whether the tested network will effectively allow for use in a chip which should desirably be connected to said wafer by bonding the chip to appropriate nodes of the wafer, and wherein the testing of a plurality of network lines determines the correct networks to interconnect to the logic inputs and outputs of said chip, and wherein the chip is bonded to the wafer at those nodes which are appropriate for its correct operation.
Claim 5
Independent Claim
124 words
A method of testing a wafer wherein said wafer has a plurality of networks of lines to be tested and each network having a node and a test lead having a terminal connected to a line coupled to said node, said test lead has a grounding point positioned adjacent the periphery of said wafer, said method comprising: placing a circumferentially disposed grounding ring in contact with said grounding points, said grounding ring being connected to ground; and contacting each node in sequence with a probe of a resistance measurement device to measure the resistance of the network lines to determine whether the measured resistance falls within expected normal inherent resistance of the measured line or is above or below the expected normal inherent resistance.
Claim 6
Independent Claim
124 words
A method of testing a wafer wherein said wafer has a plurality of networks of lines to be tested and each network having a node and a test lead having a terminal connected to a line coupled to said node, said test lead has a grounding point positioned adjacent the periphery of said wafer, said method comprising: placing a circumferentially disposed grounding ring in contact with said grounding points, said grounding ring being connected to ground; and contacting each node in sequence with a probe of a resistance measurement device to measure the resistance of the network lines to determine whether the measured resistance falls within expected normal inherent resistance of the measured line or is above or below the expected normal inherent resistance.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-04 | 1988-06-04 | 1988-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-04 | 1992-06-04 | 1992-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-04 | 1996-06-04 | 1996-12-04 | $7700.00 | Window Closed / Lapsed |