CMOS power-on reset circuit

Claim 2

A CMOS power-on reset circuit comprising: an initializing circuit having an input terminal and an output terminal, said initializing circuit providing a first constant voltage signal to said output terminal in response to a supply voltage rising above a first selected value; a delay circuit, responsive to said supply voltage for providing a first intermediate signal, said delay circuit comprising a resistive means having an output terminal and a first terminal; a capacitor having a first and a second plate, said first plate of said capacitor being connected to said output terminal of said resistive means, said second plate of said capacitor for connecting to a reference voltage; wherein said resistive means conducts if and only if said supply voltage rises above a third selected value; wherein said supply voltage is applied to said first terminal of said resistive means; wherein said first intermediate signal is provided to said output terminal of said resistive means after said supply voltage rises above said third selected value; and further wherein said first intermediate signal rises above a second selected value on said output terminal of said resistive means a selected period of time after said supply voltage rises above said first selected value such that said initializing circuit provides a first constant output signal; an inverting means having an input terminal and an output terminal, said input terminal of said inverting means being connected to said output terminal of said resistive means and said output terminal of said inverting means being connected to said input terminal of said initializing circuit, said input terminal of said inverting means receiving said first intermediate signal and said inverting means providing a second intermediate signal, complementary to said first intermediate signal, to said input terminal of said initializing circuit in response to said first intermediate signal rising above said second selected value on said output terminal of said resistive means, said second intermediate signal causing said initializing circuit to provide a second constant voltage signal to said output terminal of said initializing circuit.

Claim 3

A CMOS power-on reset circuit as in claim 1 wherein said third selected value is greater than said first

Claim 4

A CMOS power-in reset circuit as in claim 1 wherein said resistive means comprises: a first transistor having a gate, a first drain/source and a second drain/source; and, a second transistor having a gate, a first drain/souce and a second drain/source, said gate and said first drain/source of said first transistor being connected to said first terminal of said resistive means, said second drain/source of said first transistor being connected to said first drain/source of said second transistor, said gate of said second transistor for being connected to a reference voltage, said second drain/source of said second transistor being connected to said output terminal of said resistive means, said selected time period, after said supply voltage rises above said first selected value such that said initializing circuit provides a first constant output signal, being determined by the threshold voltages of said first and second transistors, the on resistances of said first and second transistors and the capacitance of said capacitor.

Claim 5

A CMOS power-on reset circuit as in claim 3 wherein said first transistor is an N channel enhancement mode transistor and wherein said second transistor is a P channel enhancement mode transistor.

Claim 6

A CMOS power-on reset circuit as in claim 1 wherein said inverting means comprises a CMOS inverter and wherein said second selected value is the trigger point of said CMOS inverter.

Claim 7

A CMOS power-on reset circuit as in claim 5 wherein said CMOS inverter comprises a P channel enhancement mode transistor and an N channel enhancement mode transistor.

Claim 8

A CMOS power-on reset circuit as in claim 1 wherein said initializing circuit comprises a CMOS inverter connected to a capacitor.

Claim 9

A CMOS power-on reset circuit comprising: an initializing circuit for providing a first constant voltage output signal in response to a supply voltage signal rising above a first selected value. a delay circuit responsive to said supply voltage signal for providing a first intermediate voltage signal, said first intermediate voltage signal rising above a second selected value a selected period of time after said supply voltage signal rises above said first selected value; and an inverting means for receiving said first intermediate signal and for providing a second intermediate signal complementary to said first intermediate signal to said initializing circuit in response to said first intermediate signal rising above said second selected value, said second intermediate signal causing said initializing circuit to provide a second constant voltage output signal, wherein said delay circuit comprises: resistive means having an output terminal and a first terminal for receiving said supply voltage signal; and a capacitor having a first and second plate, said first plate of said capacitor being connected to said output terminal of said resistive means, said second plate of said capacitor for connecting to a reference voltage, wherein said resistive means conducts if and only if said supply voltage signal rises above a third selected value; wherein said resistive means comprises: a first transistor having a gate, a first drain/source and a second drain/source; and a second transistor having a gate, a first drain/source and a second drain/source, said gate and said first drain/source of said first transistor being connected to said first terminal of said resistive means, said second drain/source of said first transistor being connected to said first drain/source of said second transistor, said gate of said second transistor for being connected to a reference voltage, said second drain/source of said second transistor being connected to said output terminal of said resistive means, said selected time period being determined by the threshold voltages of said first and second transistors, the on resistance of said first and second transistors and the capacitance of said capacitor; wherein said first transistor is an N channel enhancement mode transistor and wherein said second transistor is an unimplanted P channel enhancement mode transistor.

Claim 10

A CMOS power-on reset circuit comprising: an initializing circuit for providing a first constant voltage output signal in response to a supply voltage signal rising above a first selected value. a delay circuit responsive to said supply voltage signal for providing a first intermediate voltage signal, said first intermediate voltage signal rising above a second selected value a selected period of time after said supply voltage signal rises above said first selected value; and an inverting means for receiving said first intermediate signal and for providing a second intermediate signal complementary to said first intermediate signal to said initializing circuit in response to said first intermediate signal rising above said second selected value, said second intermediate signal causing said initializing circuit to provide a second constant voltage output signal, wherein said delay circuit comprises: resistive means having an output terminal and a first terminal for receiving said supply voltage signal; and a capacitor having a first and second plate, said first plate of said capacitor being connected to said output terminal of said resistive means, said second plate of said capacitor for connecting to a reference voltage, wherein said resistive means conducts if and only if said supply voltage signal rises above a third selected value; wherein said resistive means comprises: a first transistor having a gate, a first drain/source and a second drain/source; and a second transistor having a gate, a first drain/source and a second drain/source, said gate and said first drain/source of said first transistor being connected to said first terminal of said resistive means, said second drain/source of said first transistor being connected to said first drain/source of said second transistor, said gate of said second transistor for being connected to a reference voltage, said second drain/source of said second transistor being connected to said output terminal of said resistive means, said selected time period being determined by the threshold voltages of said first and second transistors, the on resistance of said first and second transistors and the capacitance of said capacitor; wherein said first transistor is an N channel enhancement mode transistor and wherein said second transistor is an unimplanted P channel enhancement mode transistor.

Claim 11

A CMOS power-on reset circuit as in claim 8 further comprising a discharge circuit having a first lead connected to said first plate of said capacitor and having a second lead for connecting to said supply voltage, said discharge circuit rapidly discharging said capacitor when said supply voltage becomes zero volts.

Claim 12

A CMOS power-on reset circuit as in claim 9 wherein said discharge circuit comprises an N channel enhancement mode transistor having a gate, a first source drain and a second drain/source, said first drain/source being connected to said first lead of said discharge circuit, said second source/drain being connected to said second lead of said discharge circuit, and said gate being connected to said first lead of said discharge circuit.

Claim 13

A CMOS power-on reset circuit comprising: an initializing circuit for providing a first constant voltage output signal in response to a supply voltage signal rising above a first selected value; a delay circuit responsive to said supply voltage signal for providing a first intermediate signal, said first intermediate signal rising above a second selected value a selected period of time after said supply voltage signal rises above said first selected value; and an inverting means for receiving said first intermediate signal and for providing a second intermediate signal complementary to said first intermediate signal to said initializing circuit in response to said first intermediate signal rising above said second selected value, said second intermediate signal causing said initializing circuit to provide a second constant voltage output signal, wherein said initializing circuit comprises a CMOS inverter connected to a capacitor, and wherein said CMOS inverter comprises: a P channel enhancement mode transistor having a gate, a source and a drain; an N channel enhancement mode transistor having a gate, source and a drain; and, wherein said capacitor has a first and a second plate, said first plate of said capacitor for being connected to said supply voltage signal, said second plate of said capacitor being connected to said gate of said P channel transistor and to said gate of said P channel transistor and to said gate of said N channel transistor, the source of said P channel transistor for being connected to said supply voltage, said drain of said P channel transistor being connected to said drain of said N channel transistor, said source of said N channel transistor for being connected to a reference voltage.

Claim 14

A CMOS power-on reset circuit comprising: an initializing circuit for providing a first constant voltage output signal in response to a supply voltage signal rising above a first selected value; a delay circuit responsive to said supply voltage signal for providing a first intermediate signal, said first intermediate signal rising above a second selected value a selected period of time after said supply voltage signal rises above said first selected value; and an inverting means for receiving said first intermediate signal and for providing a second intermediate signal complementary to said first intermediate signal to said initializing circuit in response to said first intermediate signal rising above said second selected value, said second intermediate signal causing said initializing circuit to provide a second constant voltage output signal, wherein said initializing circuit comprises a CMOS inverter connected to a capacitor, and wherein said CMOS inverter comprises: a P channel enhancement mode transistor having a gate, a source and a drain; an N channel enhancement mode transistor having a gate, source and a drain; and, wherein said capacitor has a first and a second plate, said first plate of said capacitor for being connected to said supply voltage signal, said second plate of said capacitor being connected to said gate of said P channel transistor and to said gate of said P channel transistor and to said gate of said N channel transistor, the source of said P channel transistor for being connected to said supply voltage, said drain of said P channel transistor being connected to said drain of said N channel transistor, said source of said N channel transistor for being connected to a reference voltage.

Claim 15

A CMOS power-on reset circuit as in claim 11 wherein the threshold voltage of said N channel enhancement mode transistor of said CMOS inverter is said first selected value.

Claim 16

A CMOS power-on reset circuit comprising: an initializing buffer having an input lead and output lead, a first power supply lead for connecting to a power supply and a second power supply lead for connecting to a reference voltage; a delay circuit having a first power supply lead for connecting to said power supply, a second power supply lead for connecting to said reference voltage and an output lead connected to said input lead of said initializing buffer, wherein said delay circuit comprises: a resistive means having a first lead connected to said first power supply lead of said delay circuit and an output lead connected to said output lead of said delay circuit; a capacitor having a first and a second plate, said first plate of said capacitor being connected to said output lead of said resistive means, said second plate of said capacitor being connected to said second power supply lead of said delay means wherein said resistive means conducts if and only if said power supply voltage rises above a third selected value; said initializing buffer providing a first constant signal on its output lead in response to a voltage on said first power supply lead rising above a first selected level; said delay circuit providing an intermediate signal on its output lead after said power supply voltage rises above said third selected value and said intermediate signal having a magnitude less than a second selected value for a first period of time greater than the time required for said voltage on said first power supply lead to rise above said first selected value such that said initializing buffer provides said first constant output signal, said intermediate signal rising above said second level after said first period of time, causing said initializing buffer to provide a second constant signal on its output lead.

Claim 17

A CMOS power-on reset circuit comprising: an initializing buffer having an input lead and output lead, a first power supply lead for connecting to a power supply and a second power supply lead for connecting to a reference voltage; a delay circuit having a first power supply lead for connecting to said power supply, a second power supply lead for connecting to said reference voltage and an output lead connected to said input lead of said initializing buffer, wherein said delay circuit comprises: a resistive means having a first lead connected to said first power supply lead of said delay circuit and an output lead connected to said output lead of said delay circuit; a capacitor having a first and a second plate, said first plate of said capacitor being connected to said output lead of said resistive means, said second plate of said capacitor being connected to said second power supply lead of said delay means wherein said resistive means conducts if and only if said power supply voltage rises above a third selected value; said initializing buffer providing a first constant signal on its output lead in response to a voltage on said first power supply lead rising above a first selected level; said delay circuit providing an intermediate signal on its output lead after said power supply voltage rises above said third selected value and said intermediate signal having a magnitude less than a second selected value for a first period of time greater than the time required for said voltage on said first power supply lead to rise above said first selected value such that said initializing buffer provides said first constant output signal, said intermediate signal rising above said second level after said first period of time, causing said initializing buffer to provide a second constant signal on its output lead.

Claim 18

A CMOS power-on reset circuit as in claim 13 wherein said resistive means comprises: a first transistor having a gate, a first drain/source and a second drain/source; and a second transistor having a gate, a first drain/source and a second drain/source, said gate and said first drain/source of said first transistor being connected to said first lead of said resistive means, said second drain/source of said first transistor being connected to said first drain/source of said second transistor, said gate of said second transistor being connected to said second power supply lead of said delay means, said second drain/source of said second transistor being connected to said output lead of said resistive means, said first time period, greater than the time required for said voltage on said first power supply lead to rise above said first selected value such that said initializing buffer provides said first constant output signal, being determined by the threshold voltages of said first and second transistors, the on resistances of said first and second transistors and the capacitance of said capacitor.

Claim 19

A CMOS power-on reset circuit as in claim 14 including a discharge circuit having a first lead connected to said first plate of said capacitor and having a second lead connected to said first power supply lead of said delay circuit, said discharge circuit rapidly discharging said capacitor when said first power supply provides a signal of 0 volts to said first power supply leads.

Claim 20

A CMOS power-on reset circuit comprising: an initializing buffer having an input lead and an output lead, a first power supply lead for connecting to a power supply and a second power supply lead for connecting to a reference voltage; and a delay circuit having a first power supply lead for connecting to said power supply, a second power supply lead for connecting to said reference voltage and an output lead connected to said input lead of said initializing buffer, said initializing buffer providing a first constant output signal in response to a voltage on said first power supply leads rising above a first selected level, said delay circuit providing an intermediate signal on its output lead having a magnitude less than a second selected level for a first period of time greater than the time required for said voltage on said first power supply leads to rise above said first selected level, said intermediate signal rising above said selected second level after said first period of time, causing said initializing buffer to provide a second constant output signal, and wherein said initializing buffer includes a first inverter having an output lead and an input lead connected to said input lead of said initializing buffer, a capacitor having a first plate connected to said first power supply lead of said initializing buffer and a second plate connected to said output lead of said first inverter; and a second inverter having an input lead connected to said second plate of said capacitor and an output lead connected to said output lead of said initializing buffer.

Claim 21

A CMOS power-on reset circuit comprising: an initializing buffer having an input lead and an output lead, a first power supply lead for connecting to a power supply and a second power supply lead for connecting to a reference voltage; and a delay circuit having a first power supply lead for connecting to said power supply, a second power supply lead for connecting to said reference voltage and an output lead connected to said input lead of said initializing buffer, said initializing buffer providing a first constant output signal in response to a voltage on said first power supply leads rising above a first selected level, said delay circuit providing an intermediate signal on its output lead having a magnitude less than a second selected level for a first period of time greater than the time required for said voltage on said first power supply leads to rise above said first selected level, said intermediate signal rising above said selected second level after said first period of time, causing said initializing buffer to provide a second constant output signal, and wherein said initializing buffer includes a first inverter having an output lead and an input lead connected to said input lead of said initializing buffer, a capacitor having a first plate connected to said first power supply lead of said initializing buffer and a second plate connected to said output lead of said first inverter; and a second inverter having an input lead connected to said second plate of said capacitor and an output lead connected to said output lead of said initializing buffer.

Claim 22

A CMOS power-on reset circuit as in claim 16 wherein said second selected value is the trigger point of said first inverter.

Claim 23

A CMOS power-on reset circuit comprising: an initializing circuit for providing a first constant voltage output signal in response to a supply voltage signal rising above a first selected value; a delay circuit responsive to said supply voltage signal for providing a first intermediate voltage signal, said first intermediate voltage signal rising above a second selected value a selected period of time after said supply voltage signal rises above said first selected value; and an inverting means for receiving said first intermediate signal and for providing a second intermediate signal complementary to said first intermediate signal to said initializing circuit in response to said first intermediate signal rising above said second selected value, said second intermediate signal causing said initializing circuit to provide a second constant voltage output signal, wherein said inverting means comprises a CMOS inverter, which in turn comprises an unimplanted P channel enhancement mode transistor and an N channel enhancement mode transistor, and wherein said second selected value is the trigger point of said CMOS inverter.

Claim 24

A CMOS power-on reset circuit comprising: an initializing circuit for providing a first constant voltage output signal in response to a supply voltage signal rising above a first selected value; a delay circuit responsive to said supply voltage signal for providing a first intermediate voltage signal, said first intermediate voltage signal rising above a second selected value a selected period of time after said supply voltage signal rises above said first selected value; and an inverting means for receiving said first intermediate signal and for providing a second intermediate signal complementary to said first intermediate signal to said initializing circuit in response to said first intermediate signal rising above said second selected value, said second intermediate signal causing said initializing circuit to provide a second constant voltage output signal, wherein said inverting means comprises a CMOS inverter, which in turn comprises an unimplanted P channel enhancement mode transistor and an N channel enhancement mode transistor, and wherein said second selected value is the trigger point of said CMOS inverter.