Semiconductor chip carrier package with a heat sink

Claim 2

A semiconductor chip carrier and contact array package comprising: (a) a first dielectric layer; (b) an aperture in said layer; (c) chip connection means, having one or more wire bond layers for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns on said one or more wire bond layers; (d) a chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess and extending through said dielectric layer aperture such that the base is exposed to ambient; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base, said chip having chip contacts connected to said metallization patterns; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending perpendicularly from said chip connection means, said contact array pin contacts extending outboard of said recess; and in which said chip connection means comprises at least two wire bond layers having connective pads at multilevels within the carrier to electrically connect said contact array thereto, said pads being electrically connected to chip leads extending from the mounted chip.

Claim 3

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) an aperture in said layer; (c) a chip connection means having one or more discrete wire bond layers for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) a chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base and connected to said metallization patterns; and (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said recess and wherein said contact array is a multipin grid array connected by through-hole plating to said chip connection means.

Claim 4

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) an aperture in said layer; (c) a chip connection means having one or more discrete wire bond layers for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) a chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base and connected to said metallization patterns; and (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said recess and wherein said contact array is a multipin grid array connected by through-hole plating to said chip connection means.

Claim 5

The invention of claim 2 comprising a multiplicity of chip-holding recesses in said one or more wire bond layers and in which said base comprises a series of base members each in contact with a mounted integrated circuit chip.

Claim 6

The invention of claim 3 in which said multiple recesses and said base members each are on opposed sides of said chip connection means so as to dissipate heat from said integrated circuit chips on both sides of the carrier.

Claim 7

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) an aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; a chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base and connected to said metallization patterns; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said recess; and (i) in which an apertured second dielectric layer is bonded to said first dielectric layer, said contact array comprising a series of pin contacts having their inner ends terminating at a level between said dielectric layers.

Claim 8

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) an aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; a chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base and connected to said metallization patterns; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said recess; and (i) in which an apertured second dielectric layer is bonded to said first dielectric layer, said contact array comprising a series of pin contacts having their inner ends terminating at a level between said dielectric layers.

Claim 9

The invention of claim 5 in which said base extends through the apertures of both said dielectric layers.

Claim 10

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) an aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) a chip-holding recess in a chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base and connected to said metallization patterns; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said recess; and (i) further comprising multiple chip-holding recesses in said wire bond layers; (j) an integrated circuit chip mounted in each of said multiple chip-holding recesses; (k) in which said base comprises a series of base members each in contact with a chip mounted in said multiple chip-holding recesses; and (l) in which said multiple chip-holding recesses and said base members each are on opposed sides of said chip connection means so as to dissipate heat from said chips in said multiple chip-holding recesses on both sides of the carrier.

Claim 11

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) an aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) a chip-holding recess in a chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base and connected to said metallization patterns; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said recess; and (i) further comprising multiple chip-holding recesses in said wire bond layers; (j) an integrated circuit chip mounted in each of said multiple chip-holding recesses; (k) in which said base comprises a series of base members each in contact with a chip mounted in said multiple chip-holding recesses; and (l) in which said multiple chip-holding recesses and said base members each are on opposed sides of said chip connection means so as to dissipate heat from said chips in said multiple chip-holding recesses on both sides of the carrier.

Claim 12

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) an aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) a chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base and connected to said metallization patterns; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said recess; and (i) further comprising means to electrically insulate an outwardly facing heat rejecting face of said base, while minimizing degradation of the thermal heat conductivity of said base.

Claim 13

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) an aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) a chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base and connected to said metallization patterns; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said recess; and (i) further comprising means to electrically insulate an outwardly facing heat rejecting face of said base, while minimizing degradation of the thermal heat conductivity of said base.

Claim 14

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) an aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) a chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base and connected to said metallization patterns; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said recess; and (i) in which said base is encapsulated with an inert electrically conductive layer.

Claim 15

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) an aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) a chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said aperture and below said chip connection means; (f) said base lying at least in part across said recess; (g) an integrated circuit chip mounted in said recess in heat-conductive contact with said base and connected to said metallization patterns; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said recess; and (i) in which said base is encapsulated with an inert electrically conductive layer.

Claim 16

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) at least one aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) at least one chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said at least one aperture and below said chip connection means; (f) said base lying at least in part across said at least one recess; (g) an integrated circuit chip mounted in said at least one recess in heat-conductive contact with said base; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple discrete metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said at least one recess; and (i) further including a cover sealingly extending over said at least one chip-holding recess.

Claim 17

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) at least one aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) at least one chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said at least one aperture and below said chip connection means; (f) said base lying at least in part across said at least one recess; (g) an integrated circuit chip mounted in said at least one recess in heat-conductive contact with said base; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple discrete metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said at least one recess; and (i) further including a cover sealingly extending over said at least one chip-holding recess.

Claim 18

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) at least one aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) at least one chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said at least one aperture and below said chip connection means; (f) said base lying at least in part across said at least one recess; (g) an integrated circuit chip mounted in said at least one recess in heat-conductive contact with said base; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple discrete metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said at least one recess; and (i) further including an insulative layer extending over said chip connection means and having a recess of greater area than and aligned with said chip-holding recess and in which said chip-holding recess is bound by a ledge for mounting additional electronic components.

Claim 19

A semiconductor chip carrier and contact array package comprising (a) a first dielectric layer; (b) at least one aperture in said layer; (c) chip connection means, having one or more discrete wire bond layers, for connecting chip contacts thereto, said chip connection means being bonded to a surface of said dielectric layer, said chip connection means including multiple discrete metallization patterns; (d) at least one chip-holding recess in said chip connection means; (e) a base of heat-conductive material extending across said at least one aperture and below said chip connection means; (f) said base lying at least in part across said at least one recess; (g) an integrated circuit chip mounted in said at least one recess in heat-conductive contact with said base; (h) a contact array of pin contacts extending to and in electrical contact with particular ones of said multiple discrete metallization patterns and extending from said chip connection means, said contact array pin contacts extending outboard of said at least one recess; and (i) further including an insulative layer extending over said chip connection means and having a recess of greater area than and aligned with said chip-holding recess and in which said chip-holding recess is bound by a ledge for mounting additional electronic components.