Thin film memory matrix using amorphous and high resistive layers

Claim 2

A matrix of nonvolatile memory cells for storing bits of data comprised of a thin film of amorphous semiconductor material overlayed by a thin film of resistive material, a plurality of parallel ohmic contact strips on the surface of said resistive material opposite said amorphous semiconductor material, a plurality of parallel ohmic contact strips on the surface of said semiconductor material opposite said resistive material and perpendicular to said contact strips on said thin film of resistive material, and means for applying a pulse of electrical energy through said thin film of amorphous semiconductor material and said overyling resistive material through said contacts, said pulse being sufficient voltage to switch said amorphous semiconductor material from a high state to a low state of resistance, and for thereafter applying a pulse of electrical current sufficient to sense the state of said semiconductor material.

Claim 3

A nonvolatile memory cell as defined in claim 1 wherein said amorphous semiconductor material is comprised of hydrogenated semiconductor material.

Claim 4

A nonvolatile memory cell as defined in claim 2 wherein said hydrogenated semiconductor material is hydrogenated silicon.

Claim 5

A nonvolatile memory cell as defined in claim 1 wherein said thin film of resistive material is comprised of tin oxide.

Claim 6

An array of memory cells comprised of a substrate of nonconductive material, a first array of parallel conductors deposited on said substrate, a thin film of amorphous semiconductor material deposited on said substrate over all said first array of conductors, a thin film of resistive material deposited over all said thin film of amophous semiconductor material, a second array of parallel conductors deposited on said thin film of resistive material, said second array of conductors being oriented perpendicular to said first array of conductors, whereby an electrical store pulse may be applied through selected conductors of said first and second arrays to said amorphous semiconductor material at the intersection of said selected conductors, said store pulse being of sufficient energy to swtich said amorphous semiconductor material to a low resistance state, and thereafter an electrical read pluse of lower energy than said store pulse, and sufficient to switch said amorphous material to a low resistance state, may be applied through said selected conductors and said amorphous semiconductor material in series with said thin film of resistive material to determine the state of said amorphous semiconductor material.

Claim 7

An array of memory cells comprised of a substrate of nonconductive material, a first array of parallel conductors deposited on said substrate, a thin film of amorphous semiconductor material deposited on said substrate over all said first array of conductors, a thin film of resistive material deposited over all said thin film of amophous semiconductor material, a second array of parallel conductors deposited on said thin film of resistive material, said second array of conductors being oriented perpendicular to said first array of conductors, whereby an electrical store pulse may be applied through selected conductors of said first and second arrays to said amorphous semiconductor material at the intersection of said selected conductors, said store pulse being of sufficient energy to swtich said amorphous semiconductor material to a low resistance state, and thereafter an electrical read pluse of lower energy than said store pulse, and sufficient to switch said amorphous material to a low resistance state, may be applied through said selected conductors and said amorphous semiconductor material in series with said thin film of resistive material to determine the state of said amorphous semiconductor material.

Claim 8

An array of memory cells as defined by claim 5 wherein said amorphous semiconductor material is comprised of hydrogenated semiconductor material.

Claim 9

An array of memory cells as defined in claim 6 wherein said hydrogenated amorphous semiconductor material is hydrogenated silicon.

Claim 10

A nonvolatile memory cell as defined in claim 5 wherein said thin film of resistive material is comprised of tin oxide.

Claim 11

An array of memory cells comprised of a substrate of nonconductive material, a first array of parallel conductors deposited on said substrate, a thin film of amorphous semiconductor material deposited on said substrate over all said first array of conductors, a thin film of resistive material deposited over all said thin film of amorphous semiconductor material, a second array of parallel conductors deposited on said thin film of resistive material, said second array of conductors being oriented perpendicular to said first array of conductors, whereby an electrical store pulse may be applied through selected conductors of said first and second arrays to said amorphous semiconductor material at the intersection of said selected conductors, said store pulse being of sufficient energy to switch said amorphous semiconductor material to a low resistance state, and thereafter an electrical read pulse or lower energy than said store pulse, and sufficient to switch said amorphous material to a low resistance state, may be applied through said selected conductors and said amorphous semiconductor material in series with said thin film of resistive material to determine the state of said amorphous semiconductor material, and including an array of nonlinear active devices, one for each of said conductors of said first array, said devices each providing an input terminal for selectively energizing the conductor connected thereto for reading out data and a set of positive feedback connections from respective ones of said conductors of said second array constituting memory output lines, and further including a thresold inhibit feedback input proportional to the sum of all the currents in said second array of conductors derived from said first array of conductors selectively energized to each of said nonlinear active devices, thereby providing a synaptic network.

Claim 12

An array of memory cells comprised of a substrate of nonconductive material, a first array of parallel conductors deposited on said substrate, a thin film of amorphous semiconductor material deposited on said substrate over all said first array of conductors, a thin film of resistive material deposited over all said thin film of amorphous semiconductor material, a second array of parallel conductors deposited on said thin film of resistive material, said second array of conductors being oriented perpendicular to said first array of conductors, whereby an electrical store pulse may be applied through selected conductors of said first and second arrays to said amorphous semiconductor material at the intersection of said selected conductors, said store pulse being of sufficient energy to switch said amorphous semiconductor material to a low resistance state, and thereafter an electrical read pulse or lower energy than said store pulse, and sufficient to switch said amorphous material to a low resistance state, may be applied through said selected conductors and said amorphous semiconductor material in series with said thin film of resistive material to determine the state of said amorphous semiconductor material, and including an array of nonlinear active devices, one for each of said conductors of said first array, said devices each providing an input terminal for selectively energizing the conductor connected thereto for reading out data and a set of positive feedback connections from respective ones of said conductors of said second array constituting memory output lines, and further including a thresold inhibit feedback input proportional to the sum of all the currents in said second array of conductors derived from said first array of conductors selectively energized to each of said nonlinear active devices, thereby providing a synaptic network.

Claim 13

An array of memory cells comprised of a substrate of nonconductive material, a first array of parallel conductors deposited on said substrate, a thin film of amorphous semiconductor material deposited on said substrate over said first array of conductors, an array of parallel strips of insulating material perpendicular to said first array of conductors, a strip of conductive material over each strip of insulating material to provide a second array of conductors, a film of amorphous semiconductor material deposited on said thin film of amorphous material along the edge of each strip of insulating material and strip of conductive material to provide a current path of predetermined resistance to said thin film of amorphous material deposited on said substrate over said first array of conductors, a layer of insulating material over the entire structure thus produced on said thin film deposited on said substrate over said first array of conductors, and a layer of conductive material deposited over said layer of insulating material in sections corresponding to preselected memory blocks so as to delineate them, whereby an MIS field-effect transistor is formed at each intersection of a conductive strip of said second array with a conductive strip of said first array for selectively gating off all memory cells in selected memory sections.

Claim 14

An array of memory cells comprised of a substrate of nonconductive material, a first array of parallel conductors deposited on said substrate, a thin film of amorphous semiconductor material deposited on said substrate over said first array of conductors, an array of parallel strips of insulating material perpendicular to said first array of conductors, a strip of conductive material over each strip of insulating material to provide a second array of conductors, a film of amorphous semiconductor material deposited on said thin film of amorphous material along the edge of each strip of insulating material and strip of conductive material to provide a current path of predetermined resistance to said thin film of amorphous material deposited on said substrate over said first array of conductors, a layer of insulating material over the entire structure thus produced on said thin film deposited on said substrate over said first array of conductors, and a layer of conductive material deposited over said layer of insulating material in sections corresponding to preselected memory blocks so as to delineate them, whereby an MIS field-effect transistor is formed at each intersection of a conductive strip of said second array with a conductive strip of said first array for selectively gating off all memory cells in selected memory sections.

Claim 15

A memory system having a memory matrix comprised of a substrate of nonconductive material, a first array of parallel conductors deposited on said substrate, a thin film of amorphous semiconductor material deposited on said substrate over said first array of conductors, a thin film of resistive material deposited over said thin film of amorphous semiconductor material, a second array of parallel conductors deposited on said thin film of resistive material, said second array of conductors being oriented perpendicular to said first array of conductors, means for encoding data to be stored in said memory matrix and for selectively applying a pulse of electrical energy though said thin film of amorphous semiconductor material and said overlaying resistive material through said contacts, said energy being sufficient to switch said amorphous semiconductor material from a high state to a low state of resistance in response to each code bit, an array of nonlinear active devices, one for each of said conductors of said second array, said devices each having an input terminal for selectively energizing the conductor connected thereto for reading out data, and a positive feedback input from a separate conductor of said first array, thereby providing a synaptic network, and means for applying prompt codes to inputs of said array of nonlinear active devices for reading out stored data that most nearly corresponds to the prompt codes, whereby data read out is presented at output terminals of said array of devices.

Claim 16

A memory system having a memory matrix comprised of a substrate of nonconductive material, a first array of parallel conductors deposited on said substrate, a thin film of amorphous semiconductor material deposited on said substrate over said first array of conductors, a thin film of resistive material deposited over said thin film of amorphous semiconductor material, a second array of parallel conductors deposited on said thin film of resistive material, said second array of conductors being oriented perpendicular to said first array of conductors, means for encoding data to be stored in said memory matrix and for selectively applying a pulse of electrical energy though said thin film of amorphous semiconductor material and said overlaying resistive material through said contacts, said energy being sufficient to switch said amorphous semiconductor material from a high state to a low state of resistance in response to each code bit, an array of nonlinear active devices, one for each of said conductors of said second array, said devices each having an input terminal for selectively energizing the conductor connected thereto for reading out data, and a positive feedback input from a separate conductor of said first array, thereby providing a synaptic network, and means for applying prompt codes to inputs of said array of nonlinear active devices for reading out stored data that most nearly corresponds to the prompt codes, whereby data read out is presented at output terminals of said array of devices.

Claim 17

A memory system having a memory matrix comprised of a substrate of nonconductive material, a first array of parallel conductors deposited on said substrate, a thin film of amorphous semiconductor material deposited on said substrate over said first array of conductors, an array of parallel strips of insulating material perpendicular to said first array of conductors, a strip of conductive material over each strip of insulating material to provide a second array of conductors, a film of amorphous semiconductor material deposited on said thin film of amorphous material along the edge of each strip of insulating material and strip of conductive material to provide a current path of predetermined resistance of said film of amorphous material deposited on said substrate over said first array of conductors, a layer ofinsulating material over the entire structure thus produced on said thin film deposited on said substrate over said first array of conductors, and a layer of conductive material deposited over said layer of insulating material in sections, whereby an MIS field-effect transistor is formed at each intersection of a conductive strip of said second array with a conductive strip of said first array for selectively gatting off all memory cells in sections, means for encoding data to be stored in said memory matrix and for selectively applying a pulse of electrical energy through said thin film of amorphous semiconductor material and said overlaying resistive material through said contacts, said energy being sufficient to switch said amorphous semiconductor material from a high state to a low state of resistance in response to each code bit, an array of nonlinar active devices, one for each of said conductors of said second array, said devices each having an input terminal for selectively energizing the conductor connected thereto for reading out data, and a positive feedback input from a separate conductor of said first array, thereby providing a synaptic network, means for selectively enabling sections of said MIS field-effect transistors for storing or reading out data, and means for applying prompt codes to inputs of said array of nonlinear active devices for reading out stored data that most nearly corresponds to the prompt codes, whereby data read out is presented at output terminals of said array of devices.

Claim 18

A memory system having a memory matrix comprised of a substrate of nonconductive material, a first array of parallel conductors deposited on said substrate, a thin film of amorphous semiconductor material deposited on said substrate over said first array of conductors, an array of parallel strips of insulating material perpendicular to said first array of conductors, a strip of conductive material over each strip of insulating material to provide a second array of conductors, a film of amorphous semiconductor material deposited on said thin film of amorphous material along the edge of each strip of insulating material and strip of conductive material to provide a current path of predetermined resistance of said film of amorphous material deposited on said substrate over said first array of conductors, a layer ofinsulating material over the entire structure thus produced on said thin film deposited on said substrate over said first array of conductors, and a layer of conductive material deposited over said layer of insulating material in sections, whereby an MIS field-effect transistor is formed at each intersection of a conductive strip of said second array with a conductive strip of said first array for selectively gatting off all memory cells in sections, means for encoding data to be stored in said memory matrix and for selectively applying a pulse of electrical energy through said thin film of amorphous semiconductor material and said overlaying resistive material through said contacts, said energy being sufficient to switch said amorphous semiconductor material from a high state to a low state of resistance in response to each code bit, an array of nonlinar active devices, one for each of said conductors of said second array, said devices each having an input terminal for selectively energizing the conductor connected thereto for reading out data, and a positive feedback input from a separate conductor of said first array, thereby providing a synaptic network, means for selectively enabling sections of said MIS field-effect transistors for storing or reading out data, and means for applying prompt codes to inputs of said array of nonlinear active devices for reading out stored data that most nearly corresponds to the prompt codes, whereby data read out is presented at output terminals of said array of devices.