US7279732B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Enhanced atomic layer deposition
Assignee: Round Rock Research LLC
•
Filing: 2004-05-26
•
Granted: 2007-10-09
•
Expires: 2024-05-26
Abstract
Abstract A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF 5 and NH 3 . In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.
Inventors
- 👤 Shuang Meng
- 👤 Garo J. Derderian
- 👤 Gurtej Singh Sandhu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:43
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; C; C23; C23C; C23C16/00; C23C16/44; C23C16/455; C23C16/45523; C23C16/45525; C23C16/45527; C23C16/45536; C23C16/45542; C23C16/50; C23C16/515; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/01342; H10D64/685; H10D64/691; H10D64/693; H10P; H10P14/00; H10P14/40; H10P14/42; H10P14/43; H10P14/432; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/696; H10D1/711; H10D1/712; H10D64/01344; H10P14/418; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/6339; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69393
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
76 words
An integrated circuit capacitor, comprising: a first electrode; a second electrode; a dielectric intermediate the first electrode and the second electrode; and an atomic layer deposited, tantalum nitride layer adjacent to and distinct from one of the first electrode and the second electrode, the tantalum nitride barrier layer having a ratio of Ta:N of 1:1 with impurities of less than about 10%, wherein the tantalum nitride barrier layer has fluorine impurities of less than about 10%.
Claim 2
Dependent Claim
76 words
An integrated circuit capacitor, comprising: a first electrode; a second electrode; a dielectric intermediate the first electrode and the second electrode; and an atomic layer deposited, tantalum nitride layer adjacent to and distinct from one of the first electrode and the second electrode, the tantalum nitride barrier layer having a ratio of Ta:N of 1:1 with impurities of less than about 10%, wherein the tantalum nitride barrier layer has fluorine impurities of less than about 10%.
Claim 3
Dependent Claim
21 words
The capacitor of claim 1 , wherein the at least one of the first electrode and the second electrode include platinum.
Claim 4
Dependent Claim
21 words
The capacitor of claim 1 , wherein the at least one of the first electrode and the second electrode include rhodium.
Claim 5
Dependent Claim
58 words
The capacitor of claim 1 , wherein the dielectric layer includes at least one of Ba Z Sr (1-z) TiO 3 [BST; where 0<z<1], BaTiO 3 , SrTiO 3 , PbTiO 3 , Pb(Zr,Ti)O 3 [PZT], (Pb,La)(Zr,Ti)O 3 [PLZT], (Pb,La)TiO 3 [PLT], Ta 2 O 5 , KNO 3 , Al 2 O 3 and LiNbO 3 .
Claim 6
Dependent Claim
26 words
The capacitor of claim 1 , wherein the dielectric layer includes at least one of a high k oxide, a multilayer oxide and a doped oxide.
Claim 7
Dependent Claim
20 words
The capacitor of claim 1 , wherein the first electrode includes a metal and the second electrode includes a metal.
Claim 8
Dependent Claim
17 words
The capacitor of claim 1 , wherein the tantalum nitride barrier layer is a diffusion baffler layer.
Claim 9
Dependent Claim
18 words
The capacitor of claim 1 , wherein the tantalum nitride barrier layer is an oxygen diffusion baffler layer.
Claim 10
Dependent Claim
25 words
The capacitor of claim 1 , wherein the first electrode, the second electrode, the dielectric, and the tantalum nitride baffler layer form a memory cell.
Claim 11
Dependent Claim
66 words
An integrated circuit transistor, comprising: a source; a drain; a gate; and an atomic layer deposited, tantalum nitride layer adjacent to and distinct from at least one of the source, the drain and the gate, the tantalum nitride layer having a ratio of Ta:N of 1:1 with impurities of less than about 10%, wherein the tantalum nitride layer has fluorine impurities of less than about 10%.
Claim 12
Dependent Claim
66 words
An integrated circuit transistor, comprising: a source; a drain; a gate; and an atomic layer deposited, tantalum nitride layer adjacent to and distinct from at least one of the source, the drain and the gate, the tantalum nitride layer having a ratio of Ta:N of 1:1 with impurities of less than about 10%, wherein the tantalum nitride layer has fluorine impurities of less than about 10%.
Claim 13
Dependent Claim
16 words
The transistor of claim 10 , wherein the tantalum nitride layer is a diffusion barrier layer.
Claim 14
Dependent Claim
17 words
The transistor of claim 10 , wherein the tantalum nitride layer is an oxygen diffusion barrier layer.
Claim 15
Dependent Claim
54 words
An integrated circuit capacitor, comprising: a first electrode; a second electrode; a dielectric intermediate the first electrode and the second electrode; and an atomic layer deposited, tantalum nitride layer adjacent at least one of the first electrode and the second electrode, wherein the tantalum nitride layer has fluorine impurities of less than about 10%.
Claim 16
Dependent Claim
54 words
An integrated circuit capacitor, comprising: a first electrode; a second electrode; a dielectric intermediate the first electrode and the second electrode; and an atomic layer deposited, tantalum nitride layer adjacent at least one of the first electrode and the second electrode, wherein the tantalum nitride layer has fluorine impurities of less than about 10%.
Claim 17
Dependent Claim
21 words
The capacitor of claim 13 , wherein the at least one of the first electrode and the second electrode include platinum.
Claim 18
Dependent Claim
21 words
The capacitor of claim 13 , wherein the at least one of the first electrode and the second electrode include rhodium.
Claim 19
Dependent Claim
58 words
The capacitor of claim 13 , wherein the dielectric layer includes at least one of Ba z Sr (1-z) TiO 3 [BST; where 0<z<1], BaTiO 3 , SrTiO 3 , PbTiO 3 , Pb(Zr,Ti)O 3 , (Pb,La)(Zr,Ti)O 3 , (Pb,La)TiO 3 , Ta 2 O 5 , KNO 3 , Al 2 O 3 and LiNbO 3 .
Claim 20
Dependent Claim
19 words
The capacitor of claim 13 , wherein the dielectric layer includes at least one of a high k oxide.
Claim 21
Dependent Claim
20 words
The capacitor of claim 13 , wherein the first electrode includes a metal and the second electrode includes a metal.
Claim 22
Dependent Claim
16 words
The capacitor of claim 13 , wherein the tantalum nitride layer is a diffusion barrier layer.
Claim 23
Dependent Claim
17 words
The capacitor of claim 13 , wherein the tantalum nitride layer is an oxygen diffusion barrier layer.
Claim 24
Dependent Claim
24 words
The capacitor of claim 13 , wherein the first electrode, the second electrode, the dielectric, and the tantalum nitride layer form a memory cell.
Claim 25
Dependent Claim
18 words
The capacitor of claim 13 , wherein the tantalum nitride layer having a ratio of Ta:N of 1:1.
Claim 26
Dependent Claim
44 words
An integrated circuit transistor, comprising: a source; a drain; a gate; and an atomic layer deposited, tantalum nitride layer adjacent at least one of the source, the drain and the gate, wherein the tantalum nitride layer has fluorine impurities of less than about 10%.
Claim 27
Dependent Claim
44 words
An integrated circuit transistor, comprising: a source; a drain; a gate; and an atomic layer deposited, tantalum nitride layer adjacent at least one of the source, the drain and the gate, wherein the tantalum nitride layer has fluorine impurities of less than about 10%.
Claim 28
Dependent Claim
16 words
The transistor of claim 23 , wherein the tantalum nitride layer is a diffusion barrier layer.
Claim 29
Dependent Claim
18 words
The transistor of claim 24 , wherein the tantalum nitride layer having a ratio of Ta:N of 1:1.
Claim 30
Dependent Claim
17 words
The transistor of claim 23 , wherein the tantalum nitride layer is an oxygen diffusion barrier layer.
Claim 31
Dependent Claim
63 words
An integrated circuit capacitor, comprising: a first electrode; a second electrode; a dielectric intermediate the first electrode and the second electrode; and an atomic layer deposited, tantalum nitride layer adjacent one of the first electrode and the second electrode, the tantalum nitride layer having a ratio of Ta:N of 1:1, wherein the tantalum nitride layer has silicon impurities of less than about 5%.
Claim 32
Dependent Claim
63 words
An integrated circuit capacitor, comprising: a first electrode; a second electrode; a dielectric intermediate the first electrode and the second electrode; and an atomic layer deposited, tantalum nitride layer adjacent one of the first electrode and the second electrode, the tantalum nitride layer having a ratio of Ta:N of 1:1, wherein the tantalum nitride layer has silicon impurities of less than about 5%.
Claim 33
Dependent Claim
54 words
An integrated circuit transistor, comprising: a source; a drain; agate; and an atomic layer deposited, tantalum nitride layer adjacent at least one of the source, the drain and the gate, the tantalum nitride layer having a ratio of Ta:N of 1:1 wherein the tantalum nitride layer has silicon impurities of less than about 5%.
Claim 34
Dependent Claim
54 words
An integrated circuit transistor, comprising: a source; a drain; agate; and an atomic layer deposited, tantalum nitride layer adjacent at least one of the source, the drain and the gate, the tantalum nitride layer having a ratio of Ta:N of 1:1 wherein the tantalum nitride layer has silicon impurities of less than about 5%.
Claim 35
Dependent Claim
21 words
The capacitor of claim 27 , wherein the at least one of the first electrode and the second electrode include platinum.
Claim 36
Dependent Claim
21 words
The capacitor of claim 27 , wherein the at least one of the first electrode and the second electrode include rhodium.
Claim 37
Dependent Claim
19 words
The capacitor of claim 27 , wherein the dielectric layer includes at least one of barium, strontium and zirconium.
Claim 38
Dependent Claim
16 words
The capacitor of claim 27 , wherein the dielectric layer includes at least a doped oxide.
Claim 39
Dependent Claim
16 words
The capacitor of claim 27 , wherein the tantalum nitride layer is a diffusion barrier layer.
Claim 40
Dependent Claim
16 words
The transistor of claim 28 , wherein the dielectric layer includes at least a doped oxide.
Claim 41
Dependent Claim
17 words
The transistor of claim 28 , wherein the tantalum nitride layer is an oxygen diffusion barrier layer.
Claim 42
Dependent Claim
19 words
The transistor of claim 28 , wherein the dielectric layer includes at least one of barium, strontium and zirconium.
Claim 43
Dependent Claim
58 words
The capacitor of claim 2 , wherein the dielectric layer includes at least one of Ba z Sr (1-z) TiO 3 [BST; where 0<z<1], BaTiO 3 , SrTiO 3 , PbTiO 3 , Pb(Zr,Ti)O 3 [PZT], (Pb,La)(Zr,Ti)O 3 [PLZT], (Pb,La)TiO 3 [PLT], Ta 2 O 5 , KNO 3 , Al 2 O 3 and LiNbO 3 .
Claim 44
Dependent Claim
26 words
The capacitor of claim 2 , wherein the dielectric layer includes at least one of a high k oxide, a multilayer oxide and a doped oxide.
Claim 45
Dependent Claim
17 words
The capacitor of claim 38 , wherein the tantalum nitride barrier layer is a diffusion barrier layer.
Claim 46
Dependent Claim
20 words
The capacitor of claim 8 , wherein the first electrode includes a metal and the second electrode includes a metal.
Claim 47
Dependent Claim
18 words
The capacitor of claim 40 , wherein the tantalum nitride barrier layer is an oxygen diffusion barrier layer.
Claim 48
Dependent Claim
25 words
The capacitor of claim 41 , wherein the first electrode, the second electrode, the dielectric, and the tantalum nitride barrier layer form a memory cell.
Claim 49
Dependent Claim
17 words
The transistor of claim 11 , wherein the tantalum nitride layer is an oxygen diffusion barrier layer.
References Cited (Backward Citations)
US3381114A
Cited
US4058430A
Cited
US4215156A
Cited
US4413022A
Cited
US4333808A
Cited
US4389973A
Cited
US4399424A
Cited
US4647947A
Cited
US4757360A
Cited
US4590042A
Cited
US4920071A
Cited
US4947221A
Cited
US4767641A
Cited
JPS62199019U
Cited
US4815962A
Cited
US5006192A
Cited
US5091207A
Cited
US4993358A
Cited
US5198029A
Cited
US6057271A
Cited
US5840897A
Cited
US6110529A
Cited
US5080928A
Cited
US5262199A
Cited
US5429966A
Cited
US5810923A
Cited
US5828080A
Cited
US5822256A
Cited
US6015590A
Cited
US5595606A
Cited
US5801105A
Cited
US5795808A
Cited
US5735960A
Cited
US6387712B1
Cited
US5698022A
Cited
US6342277B1
Cited
US5916365A
Cited
US5950925A
Cited
US6059885A
Cited
US6325017B1
Cited
US5855675A
Cited
US6174377B1
Cited
US6013553A
Cited
US6020024A
Cited
US5879459A
Cited
US6281144B1
Cited
US6161500A
Cited
US5972430A
Cited
US20010048981A1
Cited
US6383955B1
Cited
US6360685B1
Cited
US6225168B1
Cited
US6302964B1
Cited
US6027961A
Cited
US6391769B1
Cited
US6211035B1
Cited
US6444895B1
Cited
US6200893B1
Cited
US6445023B1
Cited
US6380579B1
Cited
US6171900B1
Cited
US6410432B1
Cited
US6524952B1
Cited
US6206972B1
Cited
US6297539B1
Cited
US20020160125A1
Cited
US6576053B1
Cited
US6475276B1
Cited
US6727169B1
Cited
US6203613B1
Cited
US6458701B1
Cited
US6590251B2
Cited
US6303481B2
Cited
US6551399B1
Cited
US20010009695A1
Cited
US6444039B1
Cited
US6534395B2
Cited
US6482740B2
Cited
US6482733B2
Cited
US6432779B1
Cited
JP2001332546A
Cited
US20010050039A1
Cited
US6521911B2
Cited
US6737317B2
Cited
US6617634B2
Cited
US6368941B1
Cited
US6486047B2
Cited
US6468924B2
Cited
US20020089023A1
Cited
US6495436B2
Cited
US20020146916A1
Cited
US6630201B2
Cited
US6348386B1
Cited
US6448192B1
Cited
US20020155688A1
Cited
US20020155689A1
Cited
US6514828B2
Cited
US20020192974A1
Cited
US6420279B1
Cited
US6534420B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-10-08 | 2011-04-09 | 2011-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-10-08 | 2015-04-09 | 2015-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-10-08 | 2019-04-09 | 2019-10-09 | $7700.00 | Window Closed / Lapsed |