Patent US6639303B2 successfully refreshed from Google Patents.
US6639303B2
Expired / Lapsed
US
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Integrated circuits and methods for their fabrication
Assignee: Adeia Semiconductor Technologies LLC
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Filing: 1999-12-17
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Granted: 2003-10-28
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Expires: 2019-12-17
Abstract
Abstract To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 μm in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads. In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder. In some embodiments, the wafer is diced and the dice are tested before the etch. The etch and the deposition of the additional dielectric are performed on good dice only. In some embodiments, the dice are not used for vertical integration.
Inventors
- 👤 Oleg Siniaguine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:51
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D62/00; H10D62/10; H10D62/117; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0245; H10W20/0249; H10W20/20; H10W20/40; H10W72/00; H10W72/071; H10W74/00; H10W74/01; H10W90/00; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/242; H10P52/00; H10W46/00; H10W72/20; H10W72/241; H10W72/244; H10W72/29; H10W72/90; H10W72/941; H10W72/9415; H10W72/942; H10W90/20; H10W90/297; H10W90/701; H10W90/721; H10W90/722
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
155 words
An integrated circuit comprising a die or a wafer comprising: a semiconductor substrate having one or more through holes passing between a first side and a second side of the substrate, wherein at least one of the through holes widens as it goes through semiconductor material of the substrate from the second side of the substrate to the first side of the substrate; a transistor having at least a portion of which is formed over the first side of the substrate; a dielectric in each of the through holes, wherein the dielectric in each through hole protrudes out of the through hole out of the semiconductor material of the substrate on the second side; and one or more conductive contacts formed in the one or more through holes, wherein the conductive contact formed in each through hole protrudes out of the through hole out of the semiconductor material of the substrate on the second side.
Claim 2
Dependent Claim
155 words
An integrated circuit comprising a die or a wafer comprising: a semiconductor substrate having one or more through holes passing between a first side and a second side of the substrate, wherein at least one of the through holes widens as it goes through semiconductor material of the substrate from the second side of the substrate to the first side of the substrate; a transistor having at least a portion of which is formed over the first side of the substrate; a dielectric in each of the through holes, wherein the dielectric in each through hole protrudes out of the through hole out of the semiconductor material of the substrate on the second side; and one or more conductive contacts formed in the one or more through holes, wherein the conductive contact formed in each through hole protrudes out of the through hole out of the semiconductor material of the substrate on the second side.
Claim 3
Dependent Claim
36 words
The integrated circuit of claim 1 wherein the dielectric around each contact protrudes out of the semiconductor material on the second side by at least 8 μm measured in the direction perpendicular to the second side.
Claim 4
Dependent Claim
23 words
The integrated circuit of claim 1 further comprising dielectric that covers the second side but does not cover the one or more contacts.
Claim 5
Dependent Claim
38 words
The integrated circuit of claim 1 in combination with one or more other integrated circuits such that at least one of the contacts contacts a conductive contact on another integrated circuit, the combination forming a vertical integrated circuit.
Claim 6
Dependent Claim
24 words
The integrated circuit of claim 1 further comprising a first circuit element at least a portion of which is formed in the semiconductor substrate.
Claim 7
Dependent Claim
19 words
The integrated circuit of claim 5 wherein the first circuit element is a transistor, a capacitor, or a resistor.
Claim 8
Dependent Claim
100 words
The integrated circuit of claim 1 wherein the integrated circuit is manufactured using a process comprising: forming one or more openings in the first side of the substrate; forming the dielectric and the conductor in each of the one or more openings; removing material from the second side of the substrate to expose the dielectric on the second side without exposing the conductor; simultaneously etching the material of the substrate and the dielectric on the second side of the substrate by a process which etches the material of the substrate faster than the dielectric and which etches the dielectric isotropically.
Claim 9
Dependent Claim
39 words
The integrated circuit of claim 7 wherein forming one or more openings comprises forming one or more openings each of which widens as it goes from the second side of the substrate to the first side of the substrate.
Claim 10
Dependent Claim
123 words
The integrated circuit of claim 7 wherein the integrated circuit is manufactured using a process comprising: forming one or more openings in the first side of the substrate such that each of the one or more openings widens as it goes from the second side of the substrate to the first side of the substrate; forming the dielectric on the sidewalls of each opening, and forming the conductor in each opening; removing material from the second side of the substrate to expose the dielectric on the second side without exposing the conductor; simultaneously etching the material of the substrate and the dielectric on the second side of the substrate by a process which etches the material of the substrate faster than the dielectric.
Claim 11
Dependent Claim
154 words
An integrated circuit comprising a die or a wafer comprising: a semiconductor substrate having a through hole passing between a first side and a second side of the substrate, wherein the through hole widens as it goes through semiconductor material of the substrate from the second side of the substrate to the first side of the substrate; a dielectric formed in the through hole and protruding out of the through hole out of the semiconductor material of the substrate on the second side; and a conductive layer of a uniform composition formed in the through hole and separated in the through hole from the semiconductor material of the substrate by the dielectric, wherein the conductive layer protrudes out of the through hole out of the semiconductor material of the substrate on the second side farther than the dielectric but does not extend away from the through hole over the substrate on the second side.
Claim 12
Dependent Claim
154 words
An integrated circuit comprising a die or a wafer comprising: a semiconductor substrate having a through hole passing between a first side and a second side of the substrate, wherein the through hole widens as it goes through semiconductor material of the substrate from the second side of the substrate to the first side of the substrate; a dielectric formed in the through hole and protruding out of the through hole out of the semiconductor material of the substrate on the second side; and a conductive layer of a uniform composition formed in the through hole and separated in the through hole from the semiconductor material of the substrate by the dielectric, wherein the conductive layer protrudes out of the through hole out of the semiconductor material of the substrate on the second side farther than the dielectric but does not extend away from the through hole over the substrate on the second side.
Claim 13
Dependent Claim
23 words
The integrated circuit of claim 10 wherein the conductive layer extends away from the through hole over the substrate on the first side.
Claim 14
Dependent Claim
34 words
The integrated circuit of claim 10 wherein a protrusion of the conductive layer on the second side forms a contact pad available for being attached to a circuit external to the die or wafer.
Claim 15
Dependent Claim
24 words
The integrated circuit of claim 10 wherein the conductive layer protrudes on the second side farther than any dielectric in the die or wafer.
Claim 16
Dependent Claim
22 words
The integrated circuit of claim 10 comprising a transistor having at least a portion formed over the first side of the substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-10-27 | 2007-04-28 | 2007-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-10-27 | 2011-04-28 | 2011-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-10-27 | 2015-04-28 | 2015-10-28 | $7700.00 | Window Closed / Lapsed |