US6340904B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
Assignee: Round Rock Research LLC
•
Filing: 1999-05-24
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Granted: 2002-01-22
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Expires: 2019-05-24
Abstract
Abstract A clock generator circuit for an integrated circuit includes a phase detector comparing the phase of a delayed external clock signal to the phase of an internal clock signal. An error signal corresponding to the difference in phase between the two clock signals is applied to a differential amplifier where the error signal is offset by a value corresponding to the delay of an external clock signal as it is coupled to the phase detector. The offset error signal is applied to a control input of a voltage controlled oscillator which generates the internal clock signal. The phase of the internal clock signal it thus adjusted so that it is substantially the same as the phase of the external clock signal before being delayed as it is coupled to the phase detector and other circuitry in the integrated circuit. The voltage controlled oscillator is constructed to operate in a plurality of discrete frequency bands so that the offset error signal need only control the frequency of the internal clock signal over a relatively small range. The frequency band is selected by a signal from a register that is programmed by a user with data identifying the frequency of the external clock signal.
Inventors
- 👤 Troy A. Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:01
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H03K; H03K5/00; H03K5/13; H03K5/131
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
146 words
An integrated circuit to which an external clock signal is applied and which is adapted to receive a digital signal, the integrated circuit comprising: an internal circuit for generating an internal clock signal, the internal circuit including a logic gate receiving the internal clock signal and the digital signal; and a clock circuit for generating the internal clock signal, the clock circuit comprising: a locked loop generating the internal clock signal, the locked loop including a phase detector receiving the applied external clock signal and the internal clock signal and controlling the phase of the internal clock signal responsive to the difference in phase between the received external clock signal and the internal clock signal; and an offset circuit producing a predetermined offset between the phase of the internal clock signal and the phase of the received external clock signal when the locked loop is locked.
Claim 2
Dependent Claim
146 words
An integrated circuit to which an external clock signal is applied and which is adapted to receive a digital signal, the integrated circuit comprising: an internal circuit for generating an internal clock signal, the internal circuit including a logic gate receiving the internal clock signal and the digital signal; and a clock circuit for generating the internal clock signal, the clock circuit comprising: a locked loop generating the internal clock signal, the locked loop including a phase detector receiving the applied external clock signal and the internal clock signal and controlling the phase of the internal clock signal responsive to the difference in phase between the received external clock signal and the internal clock signal; and an offset circuit producing a predetermined offset between the phase of the internal clock signal and the phase of the received external clock signal when the locked loop is locked.
Claim 3
Dependent Claim
56 words
The integrated circuit of claim 1 wherein the predetermined offset comprises a phase corresponding to the difference between the phase of the external clock signal and the phase of the received external clock signal so that the phase of the internal clock signal is substantially the same as the phase of the applied external clock signal.
Claim 4
Dependent Claim
15 words
The integrated circuit of claim 1 , wherein the locked loop comprises a phase-lock loop.
Claim 5
Dependent Claim
103 words
The integrated circuit of claim 3 , wherein the clock circuit further comprising: a storage device storing data indicative of one of a plurality of predetermined frequency ranges of the applied external clock signal; and a frequency band selector circuit adapted to cause the phase-lock loop to operate in one of a plurality of discrete frequency bands corresponding, respectively, to the predetermined frequency ranges, the frequency band selector circuit being coupled to the storage device to receive the frequency range data from the storage device and to operate the phase-lock loop in a frequency band corresponding to the data from the storage device.
Claim 6
Dependent Claim
35 words
The integrated circuit of claim 4 , wherein the storage device comprises a programmable register, and wherein the clock circuit further comprises an input device adapted to input the frequency range data into the register.
Claim 7
Dependent Claim
22 words
The integrated circuit of claim 1 , wherein the internal circuit of the integrated circuit comprises a dynamic random access memory circuit.
Claim 8
Independent Claim
236 words
A method of generating an internal clock signal synchronized to an external clock signal that is coupled to a circuit in an integrated circuit, the external clock signal being delayed as it is coupled to the circuit so that the circuit receives a delayed external clock signal, the method comprising: comparing the phase of the delayed external clock signal to the phase of the internal clock signal; offsetting the comparison of the phase of the delayed external clock signal to the phase of the internal clock signal by a phase offset corresponding to the difference between the phase of the external clock signal and the phase of the delayed external clock signal; generating as the internal clock signal a signal having a phase determined by the offset comparison between the phase of the delayed external clock signal and the phase of the internal clock signal; storing data indicative of one of a plurality of predetermined frequency ranges of the external clock signal; selecting one of a plurality of discrete frequency bands of the internal clock signal corresponding, respectively to the predetermined frequency ranges, the discrete frequency band being selected based on the stored frequency range data; and adjusting the phase and frequency of the internal clock signal within the selected frequency band as a function of the offset comparison between the phase of the delayed external clock signal and the phase of the internal clock signal.
Claim 9
Independent Claim
236 words
A method of generating an internal clock signal synchronized to an external clock signal that is coupled to a circuit in an integrated circuit, the external clock signal being delayed as it is coupled to the circuit so that the circuit receives a delayed external clock signal, the method comprising: comparing the phase of the delayed external clock signal to the phase of the internal clock signal; offsetting the comparison of the phase of the delayed external clock signal to the phase of the internal clock signal by a phase offset corresponding to the difference between the phase of the external clock signal and the phase of the delayed external clock signal; generating as the internal clock signal a signal having a phase determined by the offset comparison between the phase of the delayed external clock signal and the phase of the internal clock signal; storing data indicative of one of a plurality of predetermined frequency ranges of the external clock signal; selecting one of a plurality of discrete frequency bands of the internal clock signal corresponding, respectively to the predetermined frequency ranges, the discrete frequency band being selected based on the stored frequency range data; and adjusting the phase and frequency of the internal clock signal within the selected frequency band as a function of the offset comparison between the phase of the delayed external clock signal and the phase of the internal clock signal.
Claim 10
Dependent Claim
19 words
The method of claim 7 , wherein the circuits in the integrated circuit comprise dynamic random access memory circuits.
Claim 11
Independent Claim
207 words
A method of generating an internal clock signal synchronized to an external clock signal that is coupled to a circuit in an integrated circuit, the external clock signal being delayed as it is coupled to the circuit so that the circuit receives a delayed external clock signal, the method comprising: comparing the phase of the delayed external clock signal to the phase of the internal clock signal to produce a phase error signal having a magnitude corresponding to the phase comparison; altering the magnitude of the phase error signal by a magnitude corresponding to the difference between the phase of the external clock signal and the phase of the delayed external clock signal; generating as the internal clock signal a signal having a phase determined by the altered phase error signal; storing data indicative of one of a plurality of predetermined frequency ranges of the external clock signal; selecting one of a plurality of discrete frequency bands of the internal clock signal corresponding, respectively, to the predetermined frequency ranges, the discrete frequency band being selected based on the stored frequency range data; and adjusting the phase and frequency of the internal clock signal within the selected frequency band as a function of the altered phase error signal.
Claim 12
Independent Claim
207 words
A method of generating an internal clock signal synchronized to an external clock signal that is coupled to a circuit in an integrated circuit, the external clock signal being delayed as it is coupled to the circuit so that the circuit receives a delayed external clock signal, the method comprising: comparing the phase of the delayed external clock signal to the phase of the internal clock signal to produce a phase error signal having a magnitude corresponding to the phase comparison; altering the magnitude of the phase error signal by a magnitude corresponding to the difference between the phase of the external clock signal and the phase of the delayed external clock signal; generating as the internal clock signal a signal having a phase determined by the altered phase error signal; storing data indicative of one of a plurality of predetermined frequency ranges of the external clock signal; selecting one of a plurality of discrete frequency bands of the internal clock signal corresponding, respectively, to the predetermined frequency ranges, the discrete frequency band being selected based on the stored frequency range data; and adjusting the phase and frequency of the internal clock signal within the selected frequency band as a function of the altered phase error signal.
Claim 13
Dependent Claim
19 words
The method of claim 9 , wherein the circuits in the integrated circuit comprise dynamic random access memory circuits.
Claim 14
Independent Claim
165 words
A method of stobing a digital signal applied to an integrated circuit that also receives an external clock signal, the method comprising: coupling the digital signal to a first internal circuit; coupling the external clock signal to a second internal circuit, the external clock signal being delayed as it is coupled to the second internal circuit; comparing the phase of the delayed external clock signal to the phase of an internal clock signal to produce a phase error signal having a magnitude corresponding to the phase comparison; altering the magnitude of the phase error signal by a magnitude corresponding to the difference between the phase of the external clock signal and the phase of the delayed external clock signal; generating as the internal clock signal a signal having a phase determined by the altered phase error signal; and applying the internal clock signal to the first internal circuit, the first internal circuit being operative to strobe the digital signal responsive to the internal clock signal.
Claim 15
Independent Claim
165 words
A method of stobing a digital signal applied to an integrated circuit that also receives an external clock signal, the method comprising: coupling the digital signal to a first internal circuit; coupling the external clock signal to a second internal circuit, the external clock signal being delayed as it is coupled to the second internal circuit; comparing the phase of the delayed external clock signal to the phase of an internal clock signal to produce a phase error signal having a magnitude corresponding to the phase comparison; altering the magnitude of the phase error signal by a magnitude corresponding to the difference between the phase of the external clock signal and the phase of the delayed external clock signal; generating as the internal clock signal a signal having a phase determined by the altered phase error signal; and applying the internal clock signal to the first internal circuit, the first internal circuit being operative to strobe the digital signal responsive to the internal clock signal.
Claim 16
Dependent Claim
15 words
The method of claim 11 , wherein the first internal circuit comprises a logic gate.
Claim 17
Dependent Claim
84 words
The method of claim 11 , further comprising: storing data indicative of one of a plurality of predetermined frequency ranges of the external clock signal; selecting one of a plurality of discrete frequency bands of the internal clock signal corresponding, respectively, to the predetermined frequency ranges, the discrete frequency band being selected based on the stored frequency range data; and adjusting the phase and frequency of the internal clock signal within the selected frequency band as a function of the altered phase error signal.
Claim 18
Dependent Claim
99 words
The method of claim 11 , further comprising: storing data indicative of one of a plurality of predetermined frequency ranges of the external clock signal; selecting one of a plurality of discrete frequency bands of the internal clock signal corresponding, respectively, to the predetermined frequency ranges, the discrete frequency band being selected based on the stored frequency range data; and adjusting the phase and frequency of the internal clock signal within the selected frequency band as a function of the offset comparison between the phase of the delayed external clock signal and the phase of the internal clock signal.
Claim 19
Independent Claim
147 words
A method of strobing a digital signal applied to an integrated circuit that also receives an external clock signal, the method comprising: coupling the digital signal to an internal circuit; comparing the phase of the external clock signal at a location within the integrated circuit to the phase of an internal clock signal to provide a phase error signal corresponding thereto; providing a phase offset signal having a magnitude substantially corresponding to the delay of the external clock signal as it is coupled to the location within the integrated circuit; summing the phase error signal and the phase offset signal to provide a control signal; producing as the internal clock signal a signal having a phase corresponding to the control signal; and applying the internal clock signal to the internal circuit, the internal circuit being operative to strobe the digital signal responsive to the internal clock signal.
Claim 20
Independent Claim
147 words
A method of strobing a digital signal applied to an integrated circuit that also receives an external clock signal, the method comprising: coupling the digital signal to an internal circuit; comparing the phase of the external clock signal at a location within the integrated circuit to the phase of an internal clock signal to provide a phase error signal corresponding thereto; providing a phase offset signal having a magnitude substantially corresponding to the delay of the external clock signal as it is coupled to the location within the integrated circuit; summing the phase error signal and the phase offset signal to provide a control signal; producing as the internal clock signal a signal having a phase corresponding to the control signal; and applying the internal clock signal to the internal circuit, the internal circuit being operative to strobe the digital signal responsive to the internal clock signal.
Claim 21
Dependent Claim
24 words
The method of claim 15 further comprising filtering the control signal prior to producing the signal having a phase corresponding to the control signal.
Claim 22
Dependent Claim
37 words
The method of claim 15 further comprising: determining the frequency of the external clock signal; and selecting a band of frequencies for the internal clock signal as a function of the frequency of the external clock signal.
Claim 23
Dependent Claim
13 words
The method of claim 15 wherein the internal circuit comprises a logic gate.
Claim 24
Dependent Claim
201 words
In an integrated circuit to which an external clock signal is applied, a clock circuit for generating at an internal circuit an internal clock signal, the clock circuit comprising: a locked loop generating the internal clock signal, the locked loop including a phase detector receiving the applied external clock signal and the internal clock signal and controlling the phase of the internal clock signal responsive to the difference in phase between the received external clock signal and the internal clock signal; an offset circuit producing a predetermined offset between the phase of the internal clock signal and the phase of the received external clock signal when the locked loop is locked; a storage device storing data indicative of one of a plurality of predetermined frequency ranges of the applied external clock signal; and a frequency band selector circuit adapted to cause the phase-lock loop to operate in one of a plurality of discrete frequency bands corresponding, respectively, to the predetermined frequency ranges, the frequency band selector circuit being coupled to the storage device to receive the frequency range data from the storage device and to operate the phase-lock loop in a frequency band corresponding to the data from the storage device.
Claim 25
Dependent Claim
201 words
In an integrated circuit to which an external clock signal is applied, a clock circuit for generating at an internal circuit an internal clock signal, the clock circuit comprising: a locked loop generating the internal clock signal, the locked loop including a phase detector receiving the applied external clock signal and the internal clock signal and controlling the phase of the internal clock signal responsive to the difference in phase between the received external clock signal and the internal clock signal; an offset circuit producing a predetermined offset between the phase of the internal clock signal and the phase of the received external clock signal when the locked loop is locked; a storage device storing data indicative of one of a plurality of predetermined frequency ranges of the applied external clock signal; and a frequency band selector circuit adapted to cause the phase-lock loop to operate in one of a plurality of discrete frequency bands corresponding, respectively, to the predetermined frequency ranges, the frequency band selector circuit being coupled to the storage device to receive the frequency range data from the storage device and to operate the phase-lock loop in a frequency band corresponding to the data from the storage device.
Claim 26
Dependent Claim
56 words
The clock circuit of claim 19 wherein the predetermined offset comprises a phase corresponding to the difference between the phase of the external clock signal and the phase of the received external clock signal so that the phase of the internal clock signal is substantially the same as the phase of the applied external clock signal.
Claim 27
Dependent Claim
15 words
The clock circuit of claim 19 , wherein the locked loop comprises a phase-lock loop.
Claim 28
Dependent Claim
35 words
The clock circuit of claim 21 , wherein the storage device comprises a programmable register, and wherein the clock circuit further comprises an input device adapted to input the frequency range data into the register.
Claim 29
Dependent Claim
22 words
The clock circuit of claim 19 , wherein the internal circuit of the integrated circuit comprises a dynamic random access memory circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-01-21 | 2005-07-23 | 2006-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-01-21 | 2009-07-23 | 2010-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-01-21 | 2013-07-23 | 2014-01-22 | $7700.00 | Window Closed / Lapsed |