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US6327196B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Synchronous memory device having an adjustable data clocking circuit

Assignee: Round Rock Research LLC
•
Filing: 2000-03-24
•
Granted: 2001-12-04
•
Expires: 2020-03-24
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Abstract

Abstract A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting circuit accepts a plurality of control signals each arranged to control passgates arranged in columns, with one column being controlled by a respective one of the control signals. A clock signal passes in parallel manner through a variety of delay gates, and each delay gate is coupled in series with one of the passgates. By selecting a path through desired passgates, one delay path is selected and the delay time added to the clock signal. This delayed clock signal is used to control the data passing circuit, which controls when data is output to the output terminals relative to the original clock signal. The control signals are created by selectively coupling or decoupling the control signals from a static voltage, and fuses or antifuses can be used to facilitate this coupling or decoupling.

Inventors

  • 👤 Patrick J. Mullarkey

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 23:47
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F2205/00; G06F2205/10; G06F2205/104

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 283 words
A synchronous memory device comprising: an address bus; a control bus; a data bus; a clock terminal adapted to receive a clock signal; a clock enable terminal adapted to receive a clock enable signal; an address decoder coupled to the address bus; a control logic circuit coupled to the control bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, including a plurality of row lines; a plurality of pairs of first and second complementary digit lines; an array of memory cells that each have a control terminal coupled to one of the row lines and a data terminal coupled to one of the first and second complementary digit lines of one of the pairs of complementary column lines; and a data delay circuit comprising an external clock terminal adapted to receive an external clock signal having a first state and a second state, a data terminal adapted to receive a data signal, an adjustable time delay circuit having one or more control inputs each adapted to receive a control signal, the time delay circuit adapted to receive the external clock signal at a clock input and pass a delayed clock signal to an output terminal, the time between when the external clock signal changes states and when the delayed clock signal changes states determined by the control signals received at the control inputs, and a data passing circuit receiving both the data signal and the delayed clock signal, the data passing circuit adapted to pass the data signal from the data terminal to a data output terminal after the delayed clock signal changes from the first to the second state.
Claim 2
Dependent Claim 283 words
A synchronous memory device comprising: an address bus; a control bus; a data bus; a clock terminal adapted to receive a clock signal; a clock enable terminal adapted to receive a clock enable signal; an address decoder coupled to the address bus; a control logic circuit coupled to the control bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, including a plurality of row lines; a plurality of pairs of first and second complementary digit lines; an array of memory cells that each have a control terminal coupled to one of the row lines and a data terminal coupled to one of the first and second complementary digit lines of one of the pairs of complementary column lines; and a data delay circuit comprising an external clock terminal adapted to receive an external clock signal having a first state and a second state, a data terminal adapted to receive a data signal, an adjustable time delay circuit having one or more control inputs each adapted to receive a control signal, the time delay circuit adapted to receive the external clock signal at a clock input and pass a delayed clock signal to an output terminal, the time between when the external clock signal changes states and when the delayed clock signal changes states determined by the control signals received at the control inputs, and a data passing circuit receiving both the data signal and the delayed clock signal, the data passing circuit adapted to pass the data signal from the data terminal to a data output terminal after the delayed clock signal changes from the first to the second state.
Claim 3
Dependent Claim 21 words
The circuit of claim 1 wherein the control signals are generated by selectively coupling the control inputs to a reference voltage.
Claim 4
Dependent Claim 78 words
The circuit of claim 1 wherein the adjustable time delay circuit further comprises: a plurality of passgates arranged in columns, each column having a different number of passgates than any other column in the time delay circuit, the passgates in the column having the highest number of passgates in the delay circuit each coupled to a respective delay element having a respective delay value, the external clock signal coupled to and passing through each of the delay elements.
Claim 5
Dependent Claim 50 words
The circuit of claim 3 wherein the number of control inputs to the delay circuit is n, the number of columns in the time delay circuit is n, and the number of passgates in the column having the highest number of passgates in the delay circuit is 2 n .
Claim 6
Dependent Claim 17 words
The circuit of claim 1 wherein the synchronous memory device is a synchronous dynamic random access memory.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-12-03 2005-06-04 2005-12-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-12-03 2009-06-04 2009-12-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-12-03 2013-06-04 2013-12-04 $7700.00 Window Closed / Lapsed

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