US5444667A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals
Assignee: Renesas Electronics Corp
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Filing: 1994-03-31
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Granted: 1995-08-22
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Expires: 2014-03-31
Abstract
Abstract A synchronous dynamic random access memory device latches external command signals for defining the internal sequence, and an input circuit produces an internal control signal from a system clock signal and a clock enable signal for latching the external command signals, wherein the input circuit maintains the internal control signal in an active level for a predetermined time period regardless of the duty ratio of the external clock signal so that a malfunction hardly takes place.
Inventors
- 👤 Takashi Obara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:56
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
283 words
A synchronous semiconductor memory device comprising: a) a memory cell array implemented by a plurality of addressable memory cells; b) an input and output unit for supplying data bits from and to said memory cell array; c) an addressing system responsive to external address signals for selectively coupling said input and output unit with said plurality of addressable memory cells; d) a timing generator responsive to external command signals for controlling said input and output unit and said addressing system; and e) an input circuit responsive to an external clock signal and an external clock enable signal for producing a main internal control signal, said main internal control signal causing said timing generator to latch said external command signals, said input circuit having e-1) a first input stage assigned to said external clock signal, and enabled with an enable signal, said first input stage being operative to produce an internal clock signal synchronous with said external clock signal, e-2) a second input stage assigned to said external clock enable signal, and enabled with said enable signal, said second input stage being operative to produce an internal clock enable signal synchronous with said external clock enable signal, e-3) a first controller responsive to said internal clock signal for producing a first internal control signal maintained at a first level for a predetermined time period, and e-4) a second controller responsive to said first internal control signal for introducing a time delay between said internal clock enable signal and a second internal control signal, said second internal control signal allowing said first controller to produce said main internal control signal from said internal clock signal maintained at the first level for said predetermined time period.
Claim 2
Dependent Claim
283 words
A synchronous semiconductor memory device comprising: a) a memory cell array implemented by a plurality of addressable memory cells; b) an input and output unit for supplying data bits from and to said memory cell array; c) an addressing system responsive to external address signals for selectively coupling said input and output unit with said plurality of addressable memory cells; d) a timing generator responsive to external command signals for controlling said input and output unit and said addressing system; and e) an input circuit responsive to an external clock signal and an external clock enable signal for producing a main internal control signal, said main internal control signal causing said timing generator to latch said external command signals, said input circuit having e-1) a first input stage assigned to said external clock signal, and enabled with an enable signal, said first input stage being operative to produce an internal clock signal synchronous with said external clock signal, e-2) a second input stage assigned to said external clock enable signal, and enabled with said enable signal, said second input stage being operative to produce an internal clock enable signal synchronous with said external clock enable signal, e-3) a first controller responsive to said internal clock signal for producing a first internal control signal maintained at a first level for a predetermined time period, and e-4) a second controller responsive to said first internal control signal for introducing a time delay between said internal clock enable signal and a second internal control signal, said second internal control signal allowing said first controller to produce said main internal control signal from said internal clock signal maintained at the first level for said predetermined time period.
Claim 3
Dependent Claim
72 words
The synchronous semiconductor memory device as set forth in claim 1, in which further comprises f) a third controller responsive to said internal clock enable signal, said second internal control signal and a third internal control signal produced from said internal clock enable signal by said second controller for producing said enable signal, said enable signal being supplied to at least said first and second input stages for activating with electric power.
Claim 4
Dependent Claim
148 words
The synchronous semiconductor memory device as set forth in claim 1, in which said first controller comprises a first one-shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal, and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal, and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal, said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal.
Claim 5
Dependent Claim
147 words
The synchronous semiconductor memory device as set forth in claim 2, in which said first controller comprises a first one-shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal, and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal, and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal, said delay circuit of said second one-shot pulse generator having a logic gate enabled with said second internal control signal.
Claim 6
Dependent Claim
66 words
The synchronous semiconductor memory device as set forth in claim 4, in which said second controller comprises a first delayed circuit responsive to said first internal control signal for producing said third internal control signal from said internal clock enable signal, and a second delayed circuit responsive to said first internal control signal for producing said second internal control signal from said third internal control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-21 | 1999-02-20 | 1999-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-21 | 2003-02-20 | 2003-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-21 | 2007-02-20 | 2007-08-22 | $7700.00 | Window Closed / Lapsed |