US5018111A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timing circuit for memory employing reset function
Assignee: Intel Corp
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Filing: 1988-12-27
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Granted: 1991-05-21
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Expires: 2008-12-27
Abstract
Abstract A timing circuit is described for a single phase clocked memory. The output of a flip-flop is used to initiate the generation of a plurality of control signals through models of circuit elements of the memory such as the word line, bit line, etc. The output of these models are used to generate control signals both when the flip-flop is set and reset. The flip-flop is reset by a signal from one of the models.
Inventors
- 👤 Paul D. Madland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:38
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G11; G11C; G11C7/00; G11C7/22; G11C8/00; G11C8/18; H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03K5/15; H03K5/15013
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
201 words
A timing circuit for providing a plurality of control signals to control accessing of data from or to a memory comprising: a first circuit means for receiving a first input signal and for providing a first output response to said first input signal; a plurality of second circuit means each representing scaled versions of actual memory components and each for providing a timed delay earlier in time to the actual delay in memory, said timed delay representing the time required for performing a function needed to access said memory, said plurality of second circuit means being coupled in series, the first one of said plurality of second circuit means being coupled to receive said first output signal, the last one of said plurality of second circuit means being coupled to provide a second input signal to said first circuit means; said first circuit means providing a second output signal in response to said second input signal; said first output signal and said second output signal each being delayed by at least one of said plurality of second circuit means, and after being so delayed, each being coupled to provide at least one of said control signals for a single memory cycle.
Claim 2
Dependent Claim
201 words
A timing circuit for providing a plurality of control signals to control accessing of data from or to a memory comprising: a first circuit means for receiving a first input signal and for providing a first output response to said first input signal; a plurality of second circuit means each representing scaled versions of actual memory components and each for providing a timed delay earlier in time to the actual delay in memory, said timed delay representing the time required for performing a function needed to access said memory, said plurality of second circuit means being coupled in series, the first one of said plurality of second circuit means being coupled to receive said first output signal, the last one of said plurality of second circuit means being coupled to provide a second input signal to said first circuit means; said first circuit means providing a second output signal in response to said second input signal; said first output signal and said second output signal each being delayed by at least one of said plurality of second circuit means, and after being so delayed, each being coupled to provide at least one of said control signals for a single memory cycle.
Claim 3
Dependent Claim
16 words
The timing circuit defined by claim 1 wherein said first circuit means comprise a bistable circuit.
Claim 4
Dependent Claim
21 words
The timing circuit defined by claim 2 wherein said second input signal comprises a reset signal to reset said bistable circuit.
Claim 5
Dependent Claim
50 words
The timing circuit defined by claim 3 wherein said first output signal and said second output signal comprise a leading edge and trailing edge of a single signal respectively, said leading edge representing a first state of said signal while the trailing edge representing a second state of said signal.
Claim 6
Dependent Claim
16 words
The timing circuit defined by claim 1 wherein one of said control signals controls address ports.
Claim 7
Dependent Claim
127 words
A timing circuit for providing a plurality of control signals to control accessing of data from a memory comprising: a flip-flop; a plurality of delay elements, each representing a scaled version of actual memory components and each for providing a timed delay, said timed delay occurring earlier in time to the actual delay in the memory, each of said delays duplicating a delay in said memory, said delay elements being coupled to said flip-flop to reset said flip-flop; the output from another of said delay elements providing a first control signal when said flip-flop is set and a second control signal when said flip-flop is reset, said first and second control signals being used to control accessing of data from said memory in a single memory cycle.
Claim 8
Dependent Claim
127 words
A timing circuit for providing a plurality of control signals to control accessing of data from a memory comprising: a flip-flop; a plurality of delay elements, each representing a scaled version of actual memory components and each for providing a timed delay, said timed delay occurring earlier in time to the actual delay in the memory, each of said delays duplicating a delay in said memory, said delay elements being coupled to said flip-flop to reset said flip-flop; the output from another of said delay elements providing a first control signal when said flip-flop is set and a second control signal when said flip-flop is reset, said first and second control signals being used to control accessing of data from said memory in a single memory cycle.
Claim 9
Dependent Claim
16 words
The timing circuit defined by claim 6 wherein another of said control signals controls address ports.
Claim 10
Dependent Claim
29 words
The timing circuit defined by claim 6 wherein said first and second control signals are triggered by the leading edge and trailing edge of a signal from said flip-flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |