Double clock frequency timing signal generator

Claim 2

A timing signal generator, comprising: a string of at least two serially connected shifting elements (22, 30; 24, 32; 26, 34; 28, 36); an inverter (38) being a loop inverter receiving an output of a shifting element on one end of said string and providing an input to a shifting element on another end of said string; each said shifting element comprising a serial connection of an inverter (30; 32; 34; 36) and two current electrodes of a transistor (22; 24; 26; 28), said transistor having a control electrode; and further comprising means (21, 23A, 23B) for applying voltages of a given phase to said control electrodes in alternate ones of said shifting elements in said string and of opposite phase to said control electrodes in ones other than said alternate ones of said shifting elements in said string.

Claim 3

A signal generator as set forth in claim 1, wherein said loop inverter (38) is either a NOR gate or a NAND gate receiving on one of its inputs said output of said shifting element on said one end of said string and on another of its inputs a reset signal.

Claim 4

A signal generator as set forth in claim 1, further comprising a plurality of signal output terminals each connected to the output of one of said shifting elements.

Claim 5

A timing signal system comprising: first and second counters (40, 44), each of said counters including: - a string of at least two serially connected shifting elements (22, 30; 24, 32; 26, 34; 28, 36); - an inverter (38; 46) being a loop inverter recei­ving an output of a shifting element on one end of said string and providing an input to a shifting element on another end of said string; - each said shifting element comprising a serial connection of an inverter (30; 32; 34; 36) and two current electrodes of a transistor (22; 24; 26; 28), said transistor having a control electrode; means (21, 23A, 23B) for applying voltages of a given phase (CT) to the control electrodes of said transistors (22, 26) in alternate ones of said shifting elements in each of said strings and of opposite phase (CC) to the control electrodes of said transistors (24, 28) in ones other than said alternate ones of said     shifting elements in each of said strings; and means (41, 42) for operating said first counter (40) at a first phase and said second counter (44) at a second phase opposite that of said first phase.

Claim 6

A timing signal system comprising: first and second counters (40, 44), each of said counters including: - a string of at least two serially connected shifting elements (22, 30; 24, 32; 26, 34; 28, 36); - an inverter (38; 46) being a loop inverter recei­ving an output of a shifting element on one end of said string and providing an input to a shifting element on another end of said string; - each said shifting element comprising a serial connection of an inverter (30; 32; 34; 36) and two current electrodes of a transistor (22; 24; 26; 28), said transistor having a control electrode; means (21, 23A, 23B) for applying voltages of a given phase (CT) to the control electrodes of said transistors (22, 26) in alternate ones of said shifting elements in each of said strings and of opposite phase (CC) to the control electrodes of said transistors (24, 28) in ones other than said alternate ones of said     shifting elements in each of said strings; and means (41, 42) for operating said first counter (40) at a first phase and said second counter (44) at a second phase opposite that of said first phase.

Claim 7

A system as set forth in claim 4, further including in each of said counters a plurality of output terminals each connected to the output of one of said shifting elements.

Claim 8

A system as set forth in claim 5, wherein said operating means (41, 42) includes means for resetting said first counter (40) at a given polarity and said second counter (44) at a polarity opposite to that of said given polarity.

Claim 9

A system as set forth in claim 4, wherein each of said inverters (30) includes an N channel device and a P channel device (65, 66).

Claim 10

A system as set forth in claim 7, wherein said transistors (22; 24) in said shifting elements are MOS transistors of a first conductivity type and are each connected in parallel respectively with another MOS transistor (68; 70) of a second conductivity type and wherein said applying means applies voltage of said opposite phase (CT) to the control electrodes of said other transistors (70) in said shifting elements which are not said alternate ones and applies voltages of said given phase to the control electrodes of said other transistors (68) in said alternate shifting elements.

Claim 11

A system as set forth in claim 5, further including a decoding circuit (48) having inputs connected to said output terminals of said first and second coun­ters.

Claim 12

A system as set forth in claim 5, further comprising a decoder (48) comprising at least one first logic gate (49) receiving signals from the output termi­nals of said alternate shifting elements but not from output terminals of shifting elements which are not said alternate shifting elements, and at least one second logic gate (49) receiving signals from the output terminals of said shifting elements which are not alter­nate shifting elements but not from the output terminals of said alternate shifting elements, said first and second logic gates producing timing signals.