Sequential timing circuitry for a semiconductor memory

Claim 2

In a semiconductor memory, having a plurality of circuit elements coupled together to selectively manipulate binary information stored within a plurality of storage cells, said circuit elements having an ordered logical sequence to manipulate said stored binary information, a timing circuit comprising: a plurality of timing generators for generating a corresponding plurality of timing signals in an order corresponding to said ordered logical sequence, said corresponding plurality of timing signals being coupled to said plurality of circuit elements, each said circuit element being responsive to at least one of said timing signals; and interconnection and triggering means for coupling predetermined ones of said timing signals from each of said timing generators to at least one other one of said plurality of timing generators, each said timing generator having a timing signal coupled thereto being activated in response to said timing signal coupled thereto, each said timing generator having a timing signal coupled thereto generating another one of said plurality of timing signals, said other timing signal generated each said timing generator having a timing signal coupled thereto being delayed in time from said timing signal coupled thereto.

Claim 3

The timing circuit of claim 1 wherein the leading edge of each of said timing signals generated by one of said timing generators having a timing signal coupled thereto is delayed in time from the leading edge of said timing signal in said ordered serial sequence coupled thereto.

Claim 4

The timing circuit of claim 1 wherein at least a first one of said timing generators is activated at least in part in response to the status of at least one of said circuit elements.

Claim 5

The timing circuit of claim 3 wherein said first timing generator is the first timing generator of said ordered serial sequence, wherein said circuit element is an address buffer such that said corresponding timing signal is generated after the output of said address buffer is valid.

Claim 6

The timing circuit of claim 1 wherein each interconnection and triggering means include a field effect transistor which causes a precharged node to be discharged in response to said activating timing goal.

Claim 7

The timing circuit of claim 5 wherein at least one of said plurality of timing generators includes: an output field effect transistor having as an output one of said plurality of timing signals; a first device for precharging the gate of said output field effect transistor, said first device coupled to the gate of said output field effect transistor; a capacitive device coupled between the gate of said output field effect transistor and a node; and means coupled to said mode, said means for charging said node and said capacitive device with respect to ground and then decoupling said node from ground in response to one other one of said timing signals coupled to said means as an input thereby causing said node to obtain a high floating potential with respect to ground.

Claim 8

In a semiconductor memory having a plurality of memory cells arranged in rows, a plurality of circuit elements including an address decoder, a sense amplifier, a plurality of memory rows selectively coupled to an input/output bus and an output buffer, a timing circuit comprising: a plurality of timing generators for generating a serial, ordered sequence of signals to activate said circuit elements; and interconnection and triggering means for coupling said sequence of timing signals in said serial and ordered sequence between a corresponding and ordered sequence of said plurality of timing generators to activate said circuit elements in a corresponding serial and ordered sequence, wherein said plurality of timing generators includes: a first generator to generate a first timing signal, CED, delayed from a chip enable signal, CE, when said address decoder has validly decoded an address of said memory; a second generator to generate a second timing signal, φ W , delayed from said and in response to said chip enable and first timing signal, CED, to activate said sense amplifiers coupled to said plurality of memory cells; a third generator to generate a third timing signal delayed from and in response to said second timing signal, φ W , and chip enable signal to couple a selected row of said plurality of memory cells to said input/output bus; and an output strobe generator to generate an output strobe timing signal delayed from and in response to said C timing signal and chip enable signal to activate said output buffer coupled to said input/output bus, whereby the circuit elements of a semi-conductor memory are enabled in a logical serial sequence without complex conditional logic circuitry to manipulate information stored within said memory with proper timing and in proper sequence.

Claim 9

In a semiconductor memory having a plurality of memory cells arranged in rows, a plurality of circuit elements including an address decoder, a sense amplifier, a plurality of memory rows selectively coupled to an input/output bus and an output buffer, a timing circuit comprising: a plurality of timing generators for generating a serial, ordered sequence of signals to activate said circuit elements; and interconnection and triggering means for coupling said sequence of timing signals in said serial and ordered sequence between a corresponding and ordered sequence of said plurality of timing generators to activate said circuit elements in a corresponding serial and ordered sequence, wherein said plurality of timing generators includes: a first generator to generate a first timing signal, CED, delayed from a chip enable signal, CE, when said address decoder has validly decoded an address of said memory; a second generator to generate a second timing signal, φ W , delayed from said and in response to said chip enable and first timing signal, CED, to activate said sense amplifiers coupled to said plurality of memory cells; a third generator to generate a third timing signal delayed from and in response to said second timing signal, φ W , and chip enable signal to couple a selected row of said plurality of memory cells to said input/output bus; and an output strobe generator to generate an output strobe timing signal delayed from and in response to said C timing signal and chip enable signal to activate said output buffer coupled to said input/output bus, whereby the circuit elements of a semi-conductor memory are enabled in a logical serial sequence without complex conditional logic circuitry to manipulate information stored within said memory with proper timing and in proper sequence.