Semiconductor memory device with internal control signal based upon output timing

Claim 1

A semiconductor memory device connectable to a power source comprising: a power source line connected to receive a power source potential from said power source; a reference potential line connected to receive a reference potential from said power source; a storage cell for storing data; an input circuit connected between said power source line and said reference potential line and receiving an external input signal having a logic level defined in reference to said reference potential to be supplied to said reference potential line, said input circuit producing an internal logic signal representing one of binary logic levels; an output circuit having a pair of output transistors connected in series between said power source line and said reference potential line and an external output terminal connected to a series connection node between said pair of output transistors, for generating an output to said external output terminal; an output drive circuit connected to said output circuit, for driving said pair of output transistors by alternately rendering one of said output transistors conductive to generate the output at said external output terminal corresponding to data read out from the storage cell at a predetermined timing when said storage cell is accessed; control pulse generating means for generating a control pulse at a timing determined in relation to said predetermined timing so that said control pulse is generated when a change of the output of said circuit occurs; and an inhibiting circuit connected to receive said control pulse and to said input circuit, said inhibiting circuit inhibiting a change of the internal logic signal of the input circuit in the binary logic levels irrespective of said external input signal when said control pulse is applied thereto, said internal logic signal of the input circuit being variable to represent either of the binary logic levels in response to said external input signal when said inhibiting circuit is not applied with said control pulse.