EP0074206A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1982-08-23
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Granted: —
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Expires: 2002-08-23
Abstract
Abstract A semiconductor memory device such as a metal-insulator semiconductor random access memory device comprises an input/output circuit having an input circuit portion (IDB) which receives input data and supplies it to a pair of data buses (DB, DB) and an output circuit portion (OPC) which amplifies signals from the pair of data buses (DB, DB) and provides output signals, and a detection circuit (CKG, G8) for detecting a change in an input address signal, the detection circuit generating an inhibit pulse (INH) having a predetermined pulse width when the input address signal changes. The input circuit portion (IDB) of the input/output circuit operates to inhibit the writing in of data during generation of the inhibit pulse (INH) even if the write-enable signal (WE) is supplied to the memory device and operates in accordance with the write-enable signal (WE) when the inhibit pulse (INH) is not generated. This prevents erroneous write-in of data occurring during switching of the address signal but, at the same time prevents the continual switching of the output transistors (Q11, Q12) of the input/output circuit and thereby increases the writing speed of the device.
Inventors
- 👤 Keizo Aoyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 23:03
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
177 words
A semiconductor memory device in which switching between a read out mode and a write-in mode is effected on the basis of a write-enable signal (WE) applied to it, the semiconductor memory device comprising a plurality of memory cells (MC); a data bus (DB,DB) operatively connected to the memory cells; an input/output circuit having an input circuit portion (IDB) which receives input data and supplies it to the data bus (DB,DB) and an output circuit portion (OPC) which outputs readout data from the data bus (DB,DB); and a detection circuit (CKG,G8) for detecting a change of an input address signal, the detection circuit (CKG,G8) generating an inhibit pulse (INH) having a predetermined pulse width when the input address signal changes, characterised in that the input circuit portion (IDB) of the input/output circuit operates to inhibit the writing in of data during the generation of the inhibit pulse (INH) even if the write-enable signal (WE) is supplied to the memory device, and operates in accordance with the write-enable signal (WE) when the inhibit pulse (INH) is not generated.
Claim 2
Dependent Claim
177 words
A semiconductor memory device in which switching between a read out mode and a write-in mode is effected on the basis of a write-enable signal (WE) applied to it, the semiconductor memory device comprising a plurality of memory cells (MC); a data bus (DB,DB) operatively connected to the memory cells; an input/output circuit having an input circuit portion (IDB) which receives input data and supplies it to the data bus (DB,DB) and an output circuit portion (OPC) which outputs readout data from the data bus (DB,DB); and a detection circuit (CKG,G8) for detecting a change of an input address signal, the detection circuit (CKG,G8) generating an inhibit pulse (INH) having a predetermined pulse width when the input address signal changes, characterised in that the input circuit portion (IDB) of the input/output circuit operates to inhibit the writing in of data during the generation of the inhibit pulse (INH) even if the write-enable signal (WE) is supplied to the memory device, and operates in accordance with the write-enable signal (WE) when the inhibit pulse (INH) is not generated.
Claim 3
Dependent Claim
123 words
A semiconductor memory device according to claim 1, wherein the input/output circuit further comprises a write-in control circuit (WCC) comprising a series connection of a load transistor (Q21) and two switching transistors (Q22, Q23), one of the two switching transistors (Q22) being controlled by the write-enable signal (WE) and the other switching transistors (Q23) being controlled by the inhibit pulse (INK from the detection circuit (CKG,G8) for detecting a change of the input address signal, and a write-in control signal (WE * ) being output and supplied from the common connection of a terminal of the load transistor (Q21) and a terminal of one of the switching transistors (Q22, Q23) to the input circuit portion of the input/output circuit to control its operation.
Claim 4
Dependent Claim
81 words
A semiconductor memory device according to claim 2, wherein the input circuit portion (IDB) of the input/output circuit comprises two inverters (Q31, Q32, Q33; Q34, Q35, Q36) which receive a non- - inverted signal and an inverted signal of the write-in data and output inverted signals of these two signals when the write-in control signal (WE*) is supplied to the inverters, and which output signals having the-same potential level when write-in control signal ( WE *) is not supplied to them.
Claim 5
Dependent Claim
79 words
A semiconductor memory device according to claim 3, wherein the two inverters each comprise a load transistor (Q31,Q34) and a parallel connection of the two switching transistors (Q32, Q33; Q35, Q36) the parallel connection being connected in series with the load transistors (Q31, Q34) and one of the two switching transistors (Q33; Q36) being controlled by the write-in control signal (WE * ) and the other (Q34;Q35) being controlled by the write-in data supplied to the semiconductor memory device.
Claim 6
Dependent Claim
32 words
A semiconductor memory device according to any one of the preceding claims, wherein the output circuit portion (OPC) is directly controlled by the write-enable signal (WE) supplied to the semiconductor memory device.
Claim 7
Dependent Claim
110 words
A semiconductor memory device according to claim 5, wherein the output circuit portion (OPC) comprises a sense amplifier. (SA) connected to the data bus (DB, DB ); two inverters (Ql3, Q14, Q15; Ql6,Q17,Ql8) which receive a non-inverted output signal and an inverted output signal from the sense amplifier (SA) and output inverted signals of these two output signals, when the write-enable signal (WE) is not supplied to the inverters and which output signals having the same potential level when the write-enable signal (WE) is supplied to them; and an output buffer circuit (Q11, Q12) whose output impedance becomes high when the two inverters output signals having the same potential level.
Claim 8
Dependent Claim
76 words
A semiconductor memory device according to claim 6, wherein the two inverters each comprise a load transistor (Q13, Q16) and a parallel connection of two switching transistors (Ql4, Q15; A17, A18) the parallel connection being connected in series with the load transistors (Q13, Q16) and one of the two switching transistors (Ql5, Q18) being controlled by the write-enable signal (WE) and the other (Q14, Q17) being controlled by the output signals from the sense amplifier (SA).
Claim 9
Dependent Claim
35 words
A semiconductor memory device according to claim 6 or 7, wherein the output buffer circuit comprises a series connection of two transistors (Q11, Q12) which are controlled by the output signals 'from the two inverters.
Claim 10
Dependent Claim
44 words
A semiconductor memory device according to any one of the preceding claims, wherein the detector circuit (CKG:G8) for detecting a change of an input address signal generates an inhibit pulse signal (INH) when 'at least one bit of the input address signal is changed.
Claim 11
Dependent Claim
70 words
A semiconductor memory device according to claim.9, wherein the circuit for detecting a change of an input address signal comprises inhibit-signal generator units (CKGo to CKGn-l) provided for each bit of the input address signal which detect any change in the one bit of the input address signal; and an OR gate (G8) which couples with the outputs from the inhibit-signal generator units to generate the inhibit pulse signal (INH).
Claim 12
Dependent Claim
32 words
A semiconductor memory device according to any one of the preceding claims, further comprising a common input/output terminal (IOP) connected to the input circuit portion (IDB) and the output circuit portion (OPC).
References Cited (Backward Citations)
No citation records indexed.
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