US5430408A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transmission gate circuit
Assignee: Texas Instruments Inc
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Filing: 1994-06-14
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Granted: 1995-07-04
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Expires: 2014-06-14
Abstract
Abstract A transmission gate circuit 20 includes a pull-up control circuit 15, a pull-down control circuit 17, and an electrical switch 19. Pull-up control circuit 15 and electrical switch 19 provide fast, complete transition from low-to-high at the output of circuit 20 thus improving circuit 20 speed as well as improving the switching speed of subsequent gates. Pull-down control circuit 17 and electrical switch 19 provide complete transition from high-to-low at the output of circuit 20. Transmission gate circuit 17 also provides increased drive such that circuit 20 may provide a gate fanout increase of 3X.
Inventors
- 👤 Kevin Ovens
- 👤 Clive Bittlestone
- 👤 Bob Helmick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:23
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/041; H03K17/04106; H03K17/51; H03K17/56; H03K17/567
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
103 words
A transmission gate circuit, comprising: an electrical switch having a first terminal connected to a voltage source, a second terminal, and a third terminal forming a circuit output; a pull-up control circuit having a first terminal forming a circuit input and a second terminal connected to the second terminal of the electrical switch; and a pull-down control circuit having a first terminal connected to the circuit input and a second terminal connected to the circuit output wherein the pull-down control circuit passes the input to the output when the input transitions from low to high during a final phase of output signal transition.
Claim 2
Dependent Claim
103 words
A transmission gate circuit, comprising: an electrical switch having a first terminal connected to a voltage source, a second terminal, and a third terminal forming a circuit output; a pull-up control circuit having a first terminal forming a circuit input and a second terminal connected to the second terminal of the electrical switch; and a pull-down control circuit having a first terminal connected to the circuit input and a second terminal connected to the circuit output wherein the pull-down control circuit passes the input to the output when the input transitions from low to high during a final phase of output signal transition.
Claim 3
Dependent Claim
36 words
The circuit of claim 1 wherein the electrical switch comprises a bipolar transistor further comprising: a base terminal forming the second terminal; a collector terminal forming the first terminal; an emitter terminal forming the third terminal.
Claim 4
Dependent Claim
15 words
The circuit of claim 1 wherein the pull-up control circuit comprises a CMOS transmission gate.
Claim 5
Dependent Claim
24 words
The circuit of claim 1 wherein the pull-up control circuit comprises a plurality of CMOS transmission gates with the gate outputs connected in parallel.
Claim 6
Dependent Claim
15 words
The circuit of claim 1 wherein the pull-down control circuit comprises a CMOS transmission gate.
Claim 7
Dependent Claim
24 words
The circuit of claim 1 wherein the pull-down control circuit comprises a plurality of CMOS transmission gates with the gate outputs connected in parallel.
Claim 8
Dependent Claim
149 words
A high speed transmission gate, comprising: a first CMOS transmission gate having a first terminal forming a circuit input, a first control terminal connected to a first enable voltage signal, a second control terminal connected to a second enable voltage signal, and a second terminal; a second CMOS transmission gate having a first terminal connected to the circuit input, a first control terminal connected to the first enable voltage signal, a second control terminal connected to the second enable voltage signal, and a second terminal forming a circuit output, wherein second CMOS transmission gate passes the input to the output when the input transitions from low to high during a final phase of output signal transition; and a bipolar transistor having a collector connected to a power supply, a base connected to the second terminal of the first CMOS transmission gate, and an emitter connected to the circuit output.
Claim 9
Dependent Claim
149 words
A high speed transmission gate, comprising: a first CMOS transmission gate having a first terminal forming a circuit input, a first control terminal connected to a first enable voltage signal, a second control terminal connected to a second enable voltage signal, and a second terminal; a second CMOS transmission gate having a first terminal connected to the circuit input, a first control terminal connected to the first enable voltage signal, a second control terminal connected to the second enable voltage signal, and a second terminal forming a circuit output, wherein second CMOS transmission gate passes the input to the output when the input transitions from low to high during a final phase of output signal transition; and a bipolar transistor having a collector connected to a power supply, a base connected to the second terminal of the first CMOS transmission gate, and an emitter connected to the circuit output.
Claim 10
Dependent Claim
14 words
The circuit of claim 7 wherein the bipolar transistor comprises an NPN bipolar transistor.
References Cited (Backward Citations)
US4890017A
Cited
US4611135A
Cited
US4571504A
Cited
US4855623A
Cited
US5036232A
Cited
US5126595A
Cited
US5055716A
Cited
US5068548A
Cited
US5055716B1
Cited
US5068548B1
Cited
US5111072A
Cited
US5243237A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-03 | 1999-01-02 | 1999-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-03 | 2003-01-02 | 2003-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-03 | 2007-01-02 | 2007-07-04 | $7700.00 | Window Closed / Lapsed |