Bi-mos semiconductor integrated circuit

Claim 2

A bi-MOS semiconductor integrated circuit comprising: a first node for receiving an input signal; an output terminal for outputting a signal; a first power supply terminal for receiving a first power supply voltage; a first bipolar transistor having a collector connected to said output terminal, an emitter connected to said first power supply terminal, and a base; and a first MOSFET having a gate connected to said first node, a drain connected to said output terminal, a source and a back gate both connected to the base of said first bipolar transistor.

Claim 3

The Bi-MOS semiconductor integrated circuit according to claim 1, wherein said first bipolar transistor is of an NPN type, and said first MOSFET is of an N-channel type.

Claim 4

The Bi-MOS semiconductor integrated circuit according to claim 1, wherein a ground voltage is applied to said first power supply terminal as the first power supply voltage.

Claim 5

The Bi-MOS semiconductor integrated circuit according to claim 1, further comprising means, inserted between the base of said first bipolar transistor and said first power supply terminal, for extracting surplus charges from the base of said first bipolar transistor.

Claim 6

The Bi-MOS semiconductor integrated circuit according to claim 1, further comprising: a second power supply terminal for receiving a second power supply voltage; a second bipolar transistor having a collector connected to aid second power supply terminal, an emitter connected to said output terminal, and a base; and a second MOSFET having a gate connected to said first node, a source connected to said second power supply terminal, and a drain connected to the base of said second bipolar transistor.

Claim 7

The Bi-MOS semiconductor integrated circuit according to claim 5, wherein said second bipolar transistor is of an NPN type, and said second MOSFET is of an P-channel type.

Claim 8

The Bi-MOS semiconductor integrated circuit according to claim 5, wherein a high voltage is applied to said second power supply terminal as the second power supply voltage.

Claim 9

The Bi-MOS semiconductor integrated circuit according to claim 5, further comprising means, inserted between the base of said second bipolar transistor and said output terminal, for extracting surplus charges from the base of said second bipolar transistor.

Claim 10

A Bi-CMOS semiconductor integrated circuit comprising: N first nodes for receiving N input signals; an output terminal for outputting a signal; a first power supply terminal for receiving a first power supply voltage; a second power supply terminal for receiving a second power supply voltage; an NPN type first bipolar transistor having a collector connected to said output terminal, an emitter connected to said first power supply terminal, and a base; N N-channel MOSFETs each having a gate, a drain, a source, and a back gate, said gate being connected to a corresponding one of said N first nodes, drain-to-source paths of said N-channel MOSFETs being connected in series between said output terminal and the base of said first bipolar transistor, and said back gate being connected to at least said source which is connected to the base of said first bipolar transistor; an NPN type second bipolar transistor having a collector connected to said second power supply terminal, an emitter connected to said output terminal, and a base; and N P-channel MOSFETs each having a gate, a drain, and a source, source-to-drain paths of said P-channel MOSFETs being connected in parallel between said second power supply terminal and said output terminal, and said gate being Connected to a corresponding one of said N first nodes.

Claim 11

A Bi-CMOS semiconductor integrated circuit comprising: N first nodes for receiving N input signals; an output terminal for outputting a signal; a first power supply terminal for receiving a first power supply voltage; a second power supply terminal for receiving a second power supply voltage; an NPN type first bipolar transistor having a collector connected to said output terminal, an emitter connected to said first power supply terminal, and a base; N N-channel MOSFETs each having a gate, a drain, a source, and a back gate, said gate being connected to a corresponding one of said N first nodes, drain-to-source paths of said N-channel MOSFETs being connected in series between said output terminal and the base of said first bipolar transistor, and said back gate being connected to at least said source which is connected to the base of said first bipolar transistor; an NPN type second bipolar transistor having a collector connected to said second power supply terminal, an emitter connected to said output terminal, and a base; and N P-channel MOSFETs each having a gate, a drain, and a source, source-to-drain paths of said P-channel MOSFETs being connected in parallel between said second power supply terminal and said output terminal, and said gate being Connected to a corresponding one of said N first nodes.

Claim 12

The Bi-CMOS semiconductor integrated circuit according to claim 9, wherein a ground voltage is applied to said first power supply terminal as the first power supply voltage, and a high voltage is applied to said second power supply terminal as the second power supply voltage.

Claim 13

The Bi-CMOS semiconductor integrated circuit according to claim 9, wherein the back gates of said N N-channel MOSFETs are connected in common to the base of said first bipolar transistor.

Claim 14

The Bi-CMOS semiconductor integrated circuit according to claim 9, further comprising: first means, inserted between the base of said first bipolar transistor and said first power supply terminal, for extracting surplus charges from the base of said first bipolar transistor; and second means, inserted between the base of said second bipolar transistor and said output terminal, for extracting surplus charges from the base of said second bipolar transistor.

Claim 15

A Bi-CMOS semiconductor integrated circuit comprising: N first nodes for receiving N input signals; an output terminal for outputting a signal; a first power supply terminal for receiving a first power supply voltage; a second power supply terminal for receiving a second power supply voltage; an NPN type first bipolar transistor having a collector connected to said output terminal, an emitter connected to said first power supply terminal, and a base; N N-channel MOSFETs each having a gate, a drain, a source, and a back gate, said gate being connected to a corresponding one of said N first nodes, drain-to-source paths of said N-channel MOSFETs being connected in parallel between said output terminal and the base of said first bipolar transistor, and said back gate being connected to said source; an NPN type second bipolar transistor having a collector connected to said second power supply terminal, an emitter connected to said output terminal, and a base; and N P-channel MOSFETs each having a gate, a drain, and a source, source-to-drain paths of said P-channel MOSFETs being connected in series between said second power supply terminal and the base of said second bipolar transistor, and said gate being connected to a corresponding one of said N first nodes.

Claim 16

A Bi-CMOS semiconductor integrated circuit comprising: N first nodes for receiving N input signals; an output terminal for outputting a signal; a first power supply terminal for receiving a first power supply voltage; a second power supply terminal for receiving a second power supply voltage; an NPN type first bipolar transistor having a collector connected to said output terminal, an emitter connected to said first power supply terminal, and a base; N N-channel MOSFETs each having a gate, a drain, a source, and a back gate, said gate being connected to a corresponding one of said N first nodes, drain-to-source paths of said N-channel MOSFETs being connected in parallel between said output terminal and the base of said first bipolar transistor, and said back gate being connected to said source; an NPN type second bipolar transistor having a collector connected to said second power supply terminal, an emitter connected to said output terminal, and a base; and N P-channel MOSFETs each having a gate, a drain, and a source, source-to-drain paths of said P-channel MOSFETs being connected in series between said second power supply terminal and the base of said second bipolar transistor, and said gate being connected to a corresponding one of said N first nodes.

Claim 17

The Bi-CMOS semiconductor integrated circuit according to claim 13 wherein a ground voltage is applied to said first power supply terminal as the first power supply voltage, and a high voltage is applied to said second power supply terminal as the second power supply voltage.

Claim 18

The Bi-CMOS semiconductor integrated circuit according to claim 13, further comprising: first means, inserted between the base of said first bipolar transistor and said first power supply terminal, for extracting surplus charges from the base of said first bipolar transistor; and second means, inserted between the base of said second bipolar transistor and said output terminal, for extracting surplus charges from the base of said second bipolar transistor.