US4880998A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bipolar transistor and CMOS transistor logic circuit having improved discharge capabilities
Assignee: Mitsubishi Electric Corp
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Filing: 1988-04-08
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Granted: 1989-11-14
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Expires: 2008-04-08
Abstract
Abstract The present invention provides a logic circuit which is formed by combination of bipolar transistors and CMOS transistors such that conduction of the bipolar transistors is controlled by the MOS transistors and an output load is charged/discharged by the conducting bipolar transistors. A logic part formed by combination of at least one or more NMOS transistors is provided between an output terminal and a low-potential power source, so that fall of output voltage in discharging is prompted by addition of discharge path through the logic part.
Inventors
- 👤 Masahiro Ueda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:13
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
219 words
A logic circuit formed by combination of a bipolar transistor and a CMOS transistor, said logic circuit comprising: an input terminal; an output terminal; a high-potential power source; a low-potential power source; a PMOS transistor having a gate connected to said input terminal and a source connected to said high-potential power source; a first resistor having an end connected to the drain of said PMOS transistor and another end connected to said output terminal: a first NPN transistor having a base connected to a node between said first resistor and said PMOS transistor, a collector connected to said high-potential power source and an emitter connected to said output terminal; a first NMOS transistor having a gate connected to said input terminal and a drain connected to said output terminal; a second resistor having an end connected to the source of said NMOS transistor and another end connected to said low-potential power source; a second NPN transistor having a base connected to a node between said second resistor and said first NMOS transistor, a collector connected to said output terminal and an emitter connected to said low-potential power source; and a second NMOS transistor having a gate directly connected to said input terminal, a drain connected to said output terminal and a source connected to said low-potential power source respectively.
Claim 2
Dependent Claim
219 words
A logic circuit formed by combination of a bipolar transistor and a CMOS transistor, said logic circuit comprising: an input terminal; an output terminal; a high-potential power source; a low-potential power source; a PMOS transistor having a gate connected to said input terminal and a source connected to said high-potential power source; a first resistor having an end connected to the drain of said PMOS transistor and another end connected to said output terminal: a first NPN transistor having a base connected to a node between said first resistor and said PMOS transistor, a collector connected to said high-potential power source and an emitter connected to said output terminal; a first NMOS transistor having a gate connected to said input terminal and a drain connected to said output terminal; a second resistor having an end connected to the source of said NMOS transistor and another end connected to said low-potential power source; a second NPN transistor having a base connected to a node between said second resistor and said first NMOS transistor, a collector connected to said output terminal and an emitter connected to said low-potential power source; and a second NMOS transistor having a gate directly connected to said input terminal, a drain connected to said output terminal and a source connected to said low-potential power source respectively.
Claim 3
Dependent Claim
314 words
A logic circuit formed by combination of bipolar transistors and CMOS transistors, said logic circuit comprising: a plurality of input terminals; an output terminal; a high-potential power source; a low-potential power source; a first logic part consisting of a sub-circuit formed by combination of a plurality of PMOS transistors and having an end connected to said high-potential power source, said PMOS transistors having gates connected to said input terminals respectively; a first resistor having an end connected to the other end of said sub-circuit of said first logic part and another end connected to said output terminal; a first NPN transistor having a base connected to a node between said first resistor and said first logic part, a collector connected to said high-potential power source and an emitter connected to said output terminal; a second logic part consisting of a sub-circuit being so formed by combination of a plurality of NMOS transistors as to be a conducting state when said first logic part is in a nonconducting state and having an end connected to said output terminal, said NMOS transistors having gates connected to said input terminals respectively; a second resistor having an end connected to the other end of said sub-circuit of said second logic part and another end connected to said low-potential power source; a second NPN transistor having a base connected to a node between said second resistor and said second logic part, a collector connected to said output terminal and an emitter connected to said low-potential power source; and a third logic part consisting of a sub-circuit being so formed by combination of a plurality of NMOS transistors as to be a conducting state when said first logic part is in a nonconducting state and parallely connected between said collector and said emitter of said second NPN transistor, said NMOS transistors having gates directly connected to said input terminals respectively.
Claim 4
Dependent Claim
314 words
A logic circuit formed by combination of bipolar transistors and CMOS transistors, said logic circuit comprising: a plurality of input terminals; an output terminal; a high-potential power source; a low-potential power source; a first logic part consisting of a sub-circuit formed by combination of a plurality of PMOS transistors and having an end connected to said high-potential power source, said PMOS transistors having gates connected to said input terminals respectively; a first resistor having an end connected to the other end of said sub-circuit of said first logic part and another end connected to said output terminal; a first NPN transistor having a base connected to a node between said first resistor and said first logic part, a collector connected to said high-potential power source and an emitter connected to said output terminal; a second logic part consisting of a sub-circuit being so formed by combination of a plurality of NMOS transistors as to be a conducting state when said first logic part is in a nonconducting state and having an end connected to said output terminal, said NMOS transistors having gates connected to said input terminals respectively; a second resistor having an end connected to the other end of said sub-circuit of said second logic part and another end connected to said low-potential power source; a second NPN transistor having a base connected to a node between said second resistor and said second logic part, a collector connected to said output terminal and an emitter connected to said low-potential power source; and a third logic part consisting of a sub-circuit being so formed by combination of a plurality of NMOS transistors as to be a conducting state when said first logic part is in a nonconducting state and parallely connected between said collector and said emitter of said second NPN transistor, said NMOS transistors having gates directly connected to said input terminals respectively.
Claim 5
Dependent Claim
52 words
A logic circuit in accordance with claim 2, wherein said first logic part is formed by a plurality of parallely connected PMOS transistors, said second logic part is formed by a plurality of serially connected NMOS transistors, and said third logic part is formed by a plurality of serially connected NMOS transistors.
Claim 6
Dependent Claim
34 words
A logic circuit in accordance with claim 3, wherein said first logic part is formed by two PMOS transistors, and each of said second and third logic parts is formed by two NMOS transistors.
Claim 7
Dependent Claim
52 words
A logic circuit in accordance with claim 2, wherein said first logic part is formed by a plurality of serially connected PMOS transistors, said second logic part is formed by a plurality of parallely connected NMOS transistors, and said third logic part is formed by a plurality of parallely connected NMOS transistors.
Claim 8
Dependent Claim
34 words
A logic circuit in accordance with claim 5, wherein said first logic part is formed by two PMOS transistors, and each of said second and third logic parts is formed by two NMOS transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-13 | 1993-05-15 | 1993-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-13 | 1997-05-15 | 1997-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-13 | 2001-05-15 | 2001-11-14 | $7700.00 | Window Closed / Lapsed |