Basic cell for bicmos gate array

Claim 2

A BiCMOS cell for use in a programmable gate array, said BiCMOS cell comprising: a plurality of P-channel transistors; a plurality of N-channel transistors; and one or more bipolar transistors, each of said one or more bipolar transistors sharing an N-well with one or more of said P-channel transistors so that said bipolar transistors may only be used as pull-up devices.

Claim 3

The BiCMOS cell of claim 1 wherein said one or more bipolar transistors comprise only one bipolar transistors.

Claim 4

The BiCMOS cell of claim 1 wherein said plurality of P-channel transistors comprises two or more sizes of P-channel transistors, where a size corresponds to a channel width, and wherein said plurality of N-channel transistors comprises three or more sizes of N-channel transistors.

Claim 5

The BiCMOS cell of claim 3 wherein said P-channel transistors comprise at least one medium size P-channel transistor and at least one small size P-channel transistor, wherein said small size P-channel transistor is smaller than said medium size P-channel transistor; and said N-channel transistors comprise at least one small size N-channel transistor, at least one medium size N-channel transistor, and at least one large size N-channel transistor, wherein said small size N-channel transistor has a greater current handling capability than said at least one medium size P-channel transistor, wherein said medium size N-channel transistor is larger than said small size N-channel transistor, and wherein said large size N-channel transistor is larger than said medium size N-channel transistor.

Claim 6

The BiCMOS cell of claim 4 wherein said one or more bipolar transistors comprise only one bipolar transistor.

Claim 7

In a programmed BiCMOS gate array, one or more macrocells having one or more bipolar transistors being used as pull-up devices and no bipolar transistors being used as pull-down devices, wherein said pull-up devices are for driving an output of said one or more macrocells to a high state.

Claim 8

In a programmed BiCMOS gate array, one or more macrocells having one or more bipolar transistors being used as pull-up devices and no bipolar transistors being used as pull-down devices, wherein said pull-up devices are for driving an output of said one or more macrocells to a high state.

Claim 9

The one or more macrocells of claim 6 further comprising one or more N-channel transistors being coupled to one or more of said bipolar transistors, said one or more N-channel transistors being used as pull-down devices for driving an output of said one or more macrocells to a low state.

Claim 10

The one or more macrocells of claim 7 wherein said one or more bipolar transistors comprise one bipolar transistor.

Claim 11

A BiCMOS cell for use in a programmable gate array, each cell comprising one or more substantially rectangular compute sections and one or more drive sections, each drive section comprising one or more bipolar transistors for use as pull-up devices in one or more macrocells, and one or more N-channel transistors for use as pull-down devices in said one or more macrocells for driving an output of said one or more macrocells to a low state, each compute section comprising components which may be interconnected to form a two-to-one multiplexer, said multiplexer having true and complement outputs, said true output being equal to a power supply voltage, said complement output being equal to ground potential.

Claim 12

A BiCMOS cell for use in a programmable gate array, each cell comprising one or more substantially rectangular compute sections and one or more drive sections, each drive section comprising one or more bipolar transistors for use as pull-up devices in one or more macrocells, and one or more N-channel transistors for use as pull-down devices in said one or more macrocells for driving an output of said one or more macrocells to a low state, each compute section comprising components which may be interconnected to form a two-to-one multiplexer, said multiplexer having true and complement outputs, said true output being equal to a power supply voltage, said complement output being equal to ground potential.

Claim 13

The BiCMOS cell of claim 9 wherein each of said compute sections contains components which may be interconnected to form a D latch having a D input terminal, a clock input terminal, and an inverted clock input terminal, such that when a clock signal applied to said clock input terminal is high, an output of said latch corresponds to a D input signal applied to said D input terminal of said latch, and when said clock signal is low, said output of said latch is unchanged.

Claim 14

The BiCMOS cell of claim 9 wherein two of said compute sections contains components which may be interconnected to form a dual port SRAM cell, each port being independently usable to read or write contents of said SRAM cell.

Claim 15

The BiCMOS cell of claim 9 wherein two of said compute sections contain components which may be interconnected to form a master/slave D flip-flop having a D input terminal, a clock input terminal, and an inverted clock input terminal.

Claim 16

The BiCMOS cell of claim 9 wherein two of said compute sections contain components which may be interconnected to form any two-input logic gate with true and complement outputs, said true output being equal to a power supply voltage, said complement output being equal to ground potential.

Claim 17

The BiCMOS cell of claim 9 wherein two of said compute sections contain components which may be interconnected to form two SRAM memory cells.

Claim 18

The BiCMOS cell of claim 9 wherein each of said drive sections further comprises one or more P-channel transistors.

Claim 19

The cell of claim 9 wherein said compute sections within said cell are identical to one another.

Claim 20

A cell for use in a mask programmable gate array, said cell comprising: one or more substantially rectangular compute sections and one or more drive sections, each of said drive sections containing one or more MOS transistors which are substantially larger than MOS transistors within said compute sections, each compute section comprising: two or more sizes of P-channel transistors, where a size corresponds to a channel width; and two or more sizes of N-channel transistors, wherein said P-channel transistors comprise at least one medium size P-channel transistor and at least one small size P-channel transistor, wherein said small size P-channel transistor is smaller than said medium size P-channel transistor; and said N-channel transistor and at least one small size N-channel transistor and at least one medium size N-channel transistor, wherein said small size N-channel transistor has a greater current handling capability than said at least one medium size P-channel transistor, and wherein said medium size N-channel transistor is larger than said small size N-channel transistor.

Claim 21

A cell for use in a mask programmable gate array, said cell comprising: one or more substantially rectangular compute sections and one or more drive sections, each of said drive sections containing one or more MOS transistors which are substantially larger than MOS transistors within said compute sections, each compute section comprising: two or more sizes of P-channel transistors, where a size corresponds to a channel width; and two or more sizes of N-channel transistors, wherein said P-channel transistors comprise at least one medium size P-channel transistor and at least one small size P-channel transistor, wherein said small size P-channel transistor is smaller than said medium size P-channel transistor; and said N-channel transistor and at least one small size N-channel transistor and at least one medium size N-channel transistor, wherein said small size N-channel transistor has a greater current handling capability than said at least one medium size P-channel transistor, and wherein said medium size N-channel transistor is larger than said small size N-channel transistor.

Claim 22

The cell of claim 17 wherein said at least one medium size N-channel transistor is at least approximately twice as large as said at least one small size N-channel transistor.

Claim 23

The cell of claim 18 wherein each of said compute sections comprises: two of said medium size P-channel transistors; one or more of said small size P-channel transistors; two of said medium size N-channel transistors; and two of said small size N-channel transistors.

Claim 24

An application Specific Integrated Circuit (ASIC), said ASIC comprising one or more arrays of BiCMOS cells and other circuitry for communicating with said arrays, said cells within said arrays of cells being programmed to form one or more logic circuit macrocells, said one or more macrocells having one or more bipolar transistors being used as pull-up devices and no bipolar transistors being used as pull-down devices.

Claim 25

An application Specific Integrated Circuit (ASIC), said ASIC comprising one or more arrays of BiCMOS cells and other circuitry for communicating with said arrays, said cells within said arrays of cells being programmed to form one or more logic circuit macrocells, said one or more macrocells having one or more bipolar transistors being used as pull-up devices and no bipolar transistors being used as pull-down devices.

Claim 26

The one or more macrocells of claim 20 further comprising one or more N-channel transistors being coupled to one or more of said bipolar transistors, said one or more N-channel transistors being used as pull-down devices for driving an output of said one or more macrocells to a low state.

Claim 27

The one or more macrocells of claim 21 wherein said one or more bipolar transistors comprise one bipolar transistor.

Claim 28

The cell of claim 17 wherein each of said drive sections comprises one or more bipolar transistors for use as pull-up devices in macrocells for driving an output of said macrocells to a high state and one or more N-channel devices for use as pull-down devices in macrocells for driving an output of said macrocells to a low state.

Claim 29

The cell of claim 23 wherein each drive section further comprises one or more P-channel transistors.

Claim 30

The BiCMOS cell of claim 1 wherein certain ones of said N-channel transistors are located within said cell so as to allow an adjacent identical BiCMOS cell in an array of BiCMOS cells to share said certain ones of said N-channel transistors.

Claim 31

The BiCMOS cell of claim 25 wherein said certain ones of said N-channel transistors are for use as additional pull-down devices in a macrocell formed by the interconnection of components in said adjacent identical cell, said pull-down devices for driving an output of said macrocell to a low state.

Claim 32

The BiCMOS cell of claim 9 wherein said N-channel transistors for use as pull-down devices are located within said cell so as to allow an adjacent identical BiCMOS cell in an array of BiCMOS cells to share said N-channel transistors.

Claim 33

The BiCMOS cell of claim 27 wherein said N-channel transistors are for use as additional pull-down devices in a macrocell formed by the interconnection of components in said adjacent identical cell, said pull-down devices for driving an output of said macrocell to a low state.

Claim 34

The cell of claim 17 wherein certain ones of said MOS transistors within said drive sections are located so as to allow an adjacent identical cell in an array of cells to share said certain ones of said MOS transistors.

Claim 35

The cell of claim 29 wherein said certain ones of said MOS transistors are for use as additional pull-down devices in a macrocell formed by the interconnection of components in said adjacent identical cell, said pull-down devices for driving an output of said macrocell to a low state.