Inverter circuit arrangements

Claim 2

An inverter circuit arrangement within a monolithic semiconductor body comprising a shallow epitaxial layer of one conductivity type on a substrate of the same conductivity type, the arrangement including at least a pair of circuit elements spaced from each other within the semiconductor body, each circuit element including a defined region of the epitaxial layer, a buried layer of opposite conductivity type at the interface between the defined region of the epitaxial layer and the substrate, a heavily doped isolation barrier of opposite conductivity type, said isolation barrier extending through the epitaxial layer into contact with the buried layer, and the defined region including a surface portion remote from the substrate, said surface portion having a part which is of said opposite conductivity type, one of said pair of circuit elements comprising a bipolar transistor with a collector comprising the combination of the buried layer and the isolation barrier, a base including an unmodified part of the defined region of the epitaxial layer, an emitter comprising the part of said opposite conductivity type of the surface portion of the defined region, the emitter being surrounded by material of said one conductivity type within the semiconductor body, and the bipolar transistor having electrode connections to the collector, the base and the emitter, the other circuit element comprising a field-effect transistor with a channel region including an unmodified part of the defined region of the epitaxial layer, the part of said opposite conductivity type of the surface portion of the defined region is contiguous with the isolation barrier, and bisects the remaining part of said one conductivity type of the surface portion into two regions, the part of said opposite conductivity type comprising the gate of the field-effect transistor, the remaining two regions of the surface portion comprising the source and the drain, and the field-effect transistor having electrode connections to the gate, the source and the drain, there also being provided within the circuit arrangement electrical connections such that the base of the bipolar transistor and the gate of the field-effect transistor are connected in common to receive input signals to the circuit arrangement, the collector of the bipolar transistor and the source of the field-effect transistor are connected in common to provide the output for the circuit arrangement, the drain of the field-effect transistor is connected to a point to be maintained at a first reference potential level, and the emitter of the bipolar transistor is connected to a point to be maintained at a second reference potential level, each input signal to the circuit arrangement to have two possible voltage levels, with one of the two possible input voltage levels causing the bipolar transistor to be switched ON and the field-effect transistor to be switched OFF, and the other of the two possible input voltage levels causing the bipolar transistor to be switched OFF and the field-effect transistor to be switched ON.

Claim 3

A circuit arrangement as set forth in claim 1 wherein said field-effect transistor is of the P-channel type and the bipolar transistor is of the NPN type, and said first reference potential level is more positive than the second reference potential level.

Claim 4

A circuit arrangement as set forth in claim 1 wherein means is connected in the input signal path for ensuring that the current level through the base region of the bipolar transistor becomes significantly larger than the minimum required for conduction of the bipolar transistor.

Claim 5

A circuit arrangement as set forth in claim 3 wherein the means connected in the input signal path comprises a parallel combination of a resistor and a capacitor.

Claim 6

A circuit arrangement as set forth in claim 3 wherein the means connected in the input signal path comprises a junction diode biased for asymmetric conduction.

Claim 7

A circuit arrangement as set forth in claim 3 wherein the means connected in the input signal path comprises a NOR gate including a plurality of junction diodes each connected to the inverter input and biased for asymmetric conduction.

Claim 8

An inverter circuit arrangement within a monolithic semiconductor body comprising a shallow epitaxial layer of one conductivity type on a substrate of the same conductivity type, the arrangement including a plurality of inverters with each inverter comprising a pair of circuit elements spaced from each other within the semiconductor body, each circuit element including a defined region of the epitaxial layer, a buried layer of opposite conductivity type at the interface between the defined region of the epitaxial layer and the substrate, a heavily doped isolation barrier of opposite conductivity type, said isolation barrier extending through the epitaxial layer into contact with the buried layer, and the defined region including a surface portion remote from the substrate, said surface portion having a part which is of said opposite conductivity type, one of said pair of circuit elements comprising a bipolar transistor with a collector comprising the combination of the buried layer and the isolation barrier, a base including an unmodified part of the defined region of the epitaxial layer, an emitter comprising the part of said opposite conductivity type of the surface portion of the defined region, the emitter being surrounded by material of said one conductivity type within the semiconductor body, and the bipolar transistor having electrode connections to the collector, the base and the emitter, the other circuit element comprising a field-effect transistor with a channel region including an unmodified part of the defined region of the epitaxial layer, the part of said opposite conductivity type of the surface portion of the defined region is contiguous with the isolation barrier, and bisects the remaining part of said one conductivity type of the surface portion into two regions, the part of said opposite conductivity type comprising the gate of the field-effect transistor, the remaining two regions of the surface portion comprising the source and the drain, and the field-effect transistor having electrode connections to the gate, the source and the drain, there also being provided within the circuit arrangement electrical connections such that the base of the bipolar transistor and the gate of the field-effect transistor are connected in common to receive input signals to the circuit arrangement, the collector of the bipolar transistor and the source of the field-effect transistor are connected in common to provide the output for the circuit arrangement, the drain of the field-effect transistor is connected to a point to be maintained at a first reference potential level, and the emitter of the bipolar transistor is connected to a point to be maintained at a second reference potential level, each input signal to the circuit arrangement to have two possible voltage levels, with one of the two possible input voltage levels causing the bipolar transistor to be switched ON and the field-effect transistor to be switched OFF, and the other of the two possible input voltage levels causing the bipolar transistor to be switched OFF and the field-effect transistor to be switched ON.

Claim 9

An inverter circuit arrangement within a monolithic semiconductor body comprising a shallow epitaxial layer of one conductivity type on a substrate of the same conductivity type, the arrangement including a plurality of inverters with each inverter comprising a pair of circuit elements spaced from each other within the semiconductor body, each circuit element including a defined region of the epitaxial layer, a buried layer of opposite conductivity type at the interface between the defined region of the epitaxial layer and the substrate, a heavily doped isolation barrier of opposite conductivity type, said isolation barrier extending through the epitaxial layer into contact with the buried layer, and the defined region including a surface portion remote from the substrate, said surface portion having a part which is of said opposite conductivity type, one of said pair of circuit elements comprising a bipolar transistor with a collector comprising the combination of the buried layer and the isolation barrier, a base including an unmodified part of the defined region of the epitaxial layer, an emitter comprising the part of said opposite conductivity type of the surface portion of the defined region, the emitter being surrounded by material of said one conductivity type within the semiconductor body, and the bipolar transistor having electrode connections to the collector, the base and the emitter, the other circuit element comprising a field-effect transistor with a channel region including an unmodified part of the defined region of the epitaxial layer, the part of said opposite conductivity type of the surface portion of the defined region is contiguous with the isolation barrier, and bisects the remaining part of said one conductivity type of the surface portion into two regions, the part of said opposite conductivity type comprising the gate of the field-effect transistor, the remaining two regions of the surface portion comprising the source and the drain, and the field-effect transistor having electrode connections to the gate, the source and the drain, there also being provided within the circuit arrangement electrical connections such that the base of the bipolar transistor and the gate of the field-effect transistor are connected in common to receive input signals to the circuit arrangement, the collector of the bipolar transistor and the source of the field-effect transistor are connected in common to provide the output for the circuit arrangement, the drain of the field-effect transistor is connected to a point to be maintained at a first reference potential level, and the emitter of the bipolar transistor is connected to a point to be maintained at a second reference potential level, each input signal to the circuit arrangement to have two possible voltage levels, with one of the two possible input voltage levels causing the bipolar transistor to be switched ON and the field-effect transistor to be switched OFF, and the other of the two possible input voltage levels causing the bipolar transistor to be switched OFF and the field-effect transistor to be switched ON.

Claim 10

A circuit arrangement as set forth in claim 7 wherein each field-effect transistor is of the P-channel type and each bipolar transistor is of the NPN type, and for each inverter said first reference potential level is more positive than the second reference potential level.

Claim 11

A circuit arrangement as set forth in claim 7 wherein separate means is connected in the input signal path for each inverter, each said means ensuring that the current level through the base region of the associated bipolar transistor becomes significantly larger than the minimum required for conduction of the bipolar transistor.

Claim 12

A circuit arrangement as set forth in claim 7 wherein the output of at least one of the inverters is connected to the input of another of the inverters.

Claim 13

A circuit arrangement as set forth in claim 10 wherein the separate outputs of at least two inverters are connected to the input of a further inverter.

Claim 14

A circuit arrangement as set forth in claim 11 wherein means is connected to the input signal path of said further inverter for ensuring that the current level through the base region of the bipolar transistor of the further inverter becomes significantly larger than the minimum required for conduction of the bipolar transistor, said means comprising a NOR gate including at least two junction diodes, the junction diodes being connected individually to the separate outputs of said at least two inverters, and are biased for asymmetric conduction.