Abstract A monolithic integrated circuit structure comprises a wafer of semiconductor material including a semiconductor substrate having an epitaxial layer of semiconductor material thereon, a first region and a second region both of a first conductivity type extending downward from a first surface of said wafer at least partially into said epitaxial layer, said first region being surrounded on all sides except said first surface by a semiconductor material of said first conductivity type of lower resistivity than the first region itself and said second region being partly surrounded by semiconductor material of said first conductivity type of lower resistivity than said second region itself, a semiconductor device of a first type formed in the first region of semiconductor material and a semiconductor device of a second type formed in the second region of semiconductor material, and a lifetime-reducing impurity located in said second region of semiconductor material whereby the switching speed of the semiconductor device of the second type in said second region is improved without substantially changing the characteristics of the semiconductor device of the first type in said first region. Typically the semiconductor device of the first type comprises an MOS device having source and drain regions and the semiconductor device of the second type comprises a bipolar transistor. The switching speed of the bipolar transistor is changed due to the fact that the second region in which the bipolar transistor is formed is not completely surrounded by the semiconductor material of said first conductivity type of lower resistivity than the second region itself.
A monolithic integrated circuit including an MOS and a bipolar transistor, which comprises: a wafer comprising a substrate of semiconductor material of P conductivity type having an epitaxial layer of semiconductor material of N conductivity type thereon; a first and a second region both of said N conductivity type included within said epitaxial layer extending downwardly from a first surface of said wafer at least partially into said epitaxial layer, said first region being surrounded on all sides except said first surface by a region of semiconductor material of said N conductivity type of lower resistivity than the first region itself and said second region being partly surrounded by semiconductor material of said N conductivity type of lower resistivity than said second region itself, wherein a portion of said lower resistivity region of semiconductor material is doped with arsenic; an MOS device having source and drain regions of said P conductivity type formed in the first region of semiconductor material; a semiconductor device of another type than MOS formed in the second region of semiconductor material; and a lifetime-reducing impurity located in said second region of semiconductor material whereby the switching speed of the semiconductor device of said other type in said second region is improved without substantially changing the characteristics of the semiconductor device of a first type in said first region.
Claim 2
Dependent Claim
223 words
A monolithic integrated circuit including an MOS and a bipolar transistor, which comprises: a wafer comprising a substrate of semiconductor material of P conductivity type having an epitaxial layer of semiconductor material of N conductivity type thereon; a first and a second region both of said N conductivity type included within said epitaxial layer extending downwardly from a first surface of said wafer at least partially into said epitaxial layer, said first region being surrounded on all sides except said first surface by a region of semiconductor material of said N conductivity type of lower resistivity than the first region itself and said second region being partly surrounded by semiconductor material of said N conductivity type of lower resistivity than said second region itself, wherein a portion of said lower resistivity region of semiconductor material is doped with arsenic; an MOS device having source and drain regions of said P conductivity type formed in the first region of semiconductor material; a semiconductor device of another type than MOS formed in the second region of semiconductor material; and a lifetime-reducing impurity located in said second region of semiconductor material whereby the switching speed of the semiconductor device of said other type in said second region is improved without substantially changing the characteristics of the semiconductor device of a first type in said first region.
Claim 3
Dependent Claim
11 words
The structure of claim 1 wherein said lifetime-reducing impurity is gold.
Claim 4
Dependent Claim
35 words
Structure as in claim 1 wherein said semiconductor device of a second type comprises a bipolar transistor having a collector region of said N conductiVity type formed in said second region of said semiconductor material.
Claim 5
Dependent Claim
47 words
Structure as in claim 1 wherein the bottom portion of said semiconductor material of said N conductivity type of lower resistivity than the first region itself surrounding said first region comprises a portion of said epitaxial layer adjacent said substrate and a contiguous portion of the substrate.
Claim 6
Dependent Claim
39 words
Structure as in claim 1 wherein the portion of said semiconductor material of said N conductivity type partly surrounding said second region comprises a portion of said epitaxial layer adjacent said substrate and the contiguous portion of said substrate.